Method and system for high integrity can bus traffic supervision in safety critical application

US11422962B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11422962-B2
Application numberUS-202017115460-A
CountryUS
Kind codeB2
Filing dateDec 8, 2020
Priority dateDec 9, 2019
Publication dateAug 23, 2022
Grant dateAug 23, 2022

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method of common controller area network (CAN) bus traffic supervision on a system having a common CAN bus, a first CAN chip and a second CAN chip, the first CAN chip and the second CAN chip are coupled together with the common CAN bus, the method includes comparing a first CAN frame received from the first CAN chip to a second CAN frame received from the second CAN chip within a CAN comparison period, and detecting a failure of at least the first CAN chip or the second CAN chip. Detecting the failure of at least the first CAN chip or the second CAN chip includes determining that the first CAN frame is not identical to the second CAN frame within the CAN comparison period.

First claim

Opening claim text (preview).

What is claimed is: 1. A system comprising: a first controller area network (CAN) system including: a first CAN chip; and a second CAN chip different from the first CAN chip; and a first common CAN bus coupled to the first CAN system, the first common CAN bus coupling the first CAN chip and the second CAN chip together; wherein the first CAN chip and the second CAN chip are configured to receive a first CAN frame from the first common CAN bus, and the first CAN system is configured to detect a failure of at least the first CAN chip or the second CAN chip, wherein the first CAN system configured to detect the failure of at least the first CAN chip or the second CAN chip comprises: the first CAN system being configured to determine that the first CAN frame is not identical to the second CAN frame. 2. The system of claim 1 , further comprising: a second CAN system including: a third CAN chip; and a fourth CAN chip different from the third CAN chip; a second common CAN bus coupled to the second CAN system, the second common CAN bus coupling the first CAN chip and the second CAN chip together; wherein the third CAN chip and the fourth CAN chip are configured to receive a second CAN frame from the second common CAN bus, and the second CAN system is configured to detect a failure of at least the third CAN chip or the fourth CAN chip. 3. The system of claim 1 , further comprising: a second CAN system coupled to the first common CAN bus, the second CAN system including: a third CAN chip; and a fourth CAN chip different from the third CAN chip; wherein the first common CAN bus further couples the third CAN chip and the fourth CAN chip together, the third CAN chip and the fourth CAN chip are configured to receive the first CAN frame from the first common CAN bus, and the second CAN system is configured to detect a failure of at least the third CAN chip or the fourth CAN chip. 4. The system of claim 1 , wherein the first CAN system further comprises: a first region including an Ethernet interface; and a first converter circuit coupled to the Ethernet interface by an Ethernet link, and configured to convert Ethernet packets into CAN frames, and the CAN frames into the Ethernet packets, the first converter circuit comprising: a first processor coupled to the Ethernet interface by the Ethernet link; the first CAN chip coupled to the first processor by a first interface; and the second CAN chip coupled to the first processor by a second interface. 5. The system of claim 1 , wherein the first CAN system further comprises: a first region including an Ethernet interface; and a first converter circuit coupled to the Ethernet interface by an Ethernet link, and configured to convert Ethernet packets into CAN frames, and the CAN frames into the Ethernet packets, the first converter circuit comprising: a first processor coupled to the Ethernet interface by the Ethernet link; and the first CAN chip coupled to the first processor by a first interface; and a second converter circuit coupled to the Ethernet interface by the Ethernet link, and configured to convert the Ethernet packets into the CAN frames, and the CAN frames into the Ethernet packets, the second converter circuit comprising: a second processor coupled to the Ethernet interface by the Ethernet link; and the second CAN chip coupled to the second processor by a second interface. 6. The system of claim 2 , further comprising: a first device coupled to the first CAN system by the first common CAN bus, the first device comprising: a fifth CAN chip coupled to the first CAN chip and the second CAN chip by the first common CAN bus; and a second device coupled to the second CAN system by the second common CAN bus, the second device comprising: a sixth CAN chip coupled to the third CAN chip and the fourth CAN chip by the second common CAN bus. 7. The system of claim 3 , further comprising: a first device coupled to the first CAN system and the second CAN system by the first common CAN bus, the first device comprising: a third CAN chip coupled to the first CAN chip, the second CAN chip, the third CAN chip and the fourth CAN chip by the first common CAN bus. 8. The system of claim 4 , wherein the first CAN chip is configured to strip a first CAN frame data payload from the first CAN frame, and is configured to send the first CAN frame data payload to the first processor by the first interface; the first processor is configured to pass the first CAN frame data payload received from the first CAN chip to the first CAN system by the Ethernet link; the second CAN chip is configured to strip a second CAN frame data payload from the first CAN frame, and is configured to send the second CAN frame data payload to the first processor by the second interface; the first processor is configured to determine a first cyclic redundancy check (CRC) on the second CAN frame data payload, and is configured to pass the first CRC to the first CAN system by the Ethernet link; and the first CAN system is configured to receive the first CAN frame data payload and the CRC, is configured to determine a second CRC based on the first CAN frame data payload, and is configured to compare the first CRC and the second CRC to each other. 9. The system of claim 8 , wherein the first CAN system is configured to determine that a failure of at least the first CAN chip or the second CAN chip occurred in response to determining that the first CRC is not identical to the second CRC; or the first CAN system is configured to determine that the failure of at least the first CAN chip or the second CAN chip did not occur in response to determining that the first CRC is identical to the second CRC. 10. A method of common controller area network (CAN) bus traffic supervision on a system having a common CAN bus, a first CAN chip and a second CAN chip, the first CAN chip and the second CAN chip are coupled together with the common CAN bus, the method comprising: comparing a first CAN frame received from the first CAN chip to a second CAN frame received from the second CAN chip within a CAN comparison period; and detecting a failure of at least the first CAN chip or the second CAN chip, wherein detecting the failure of at least the first CAN chip or the second CAN chip comprises: determining that the first CAN frame is not identical to the second CAN frame within the CAN comparison period. 11. The method of claim 10 , further comprising: switching over to a redundant system, in response to detecting the failure of at least the first CAN chip or the second CAN chip occurred. 12. The method of claim 10 , wherein detecting the failure of at least the first CAN chip or the second CAN chip, further comprises: determining that first CAN frame payload of the first CAN frame is missing or unavailable within the CAN comparison period. 13. The method of claim 10 , wherein detecting the failure of at least the first CAN chip or the second CAN chip, further comprises: determining that the first CAN frame or the second CAN frame is missing or unavailable within a CAN timeout. 14. The method of claim 10 , further comprising: determining that no failure of at least the first CAN chip or the second CAN chip occurred in response to determining that the first CAN frame is identical to the second CAN frame. 15. The method of claim 10 , wherein comparing the first CAN frame received from the first CAN chip to the second CAN frame received from the second CAN chip within the CAN comparison period, comprises: comparing a first payload of the first CAN frame to a second payl

Assignees

Inventors

Classifications

  • Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title

  • G06F13/36Primary

    for access to common bus or bus system · CPC title

  • Bus coupling · CPC title

  • by using a plurality of nodes · CPC title

  • Controller Area Network CAN · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11422962B2 cover?
A method of common controller area network (CAN) bus traffic supervision on a system having a common CAN bus, a first CAN chip and a second CAN chip, the first CAN chip and the second CAN chip are coupled together with the common CAN bus, the method includes comparing a first CAN frame received from the first CAN chip to a second CAN frame received from the second CAN chip within a CAN comparis…
Who is the assignee on this patent?
Thales Canada Inc
What technology area does this patent fall under?
Primary CPC classification G06F13/36. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 23 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).