Method and apparatus for accurate measurement of platform power

Patent metadata

Field	Value
Publication number	US-11422173-B2
Application number	US-202017109031-A
Country	US
Kind code	B2
Filing date	Dec 1, 2020
Priority date	May 9, 2020
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

A Power Management Controller (PMC) which manages power states of a platform, informs a power accumulator device to start measuring the platform power during entry into the low power state (e.g., S0iX). The power accumulator device starts measuring the power until a stop message comes from the PMC. The PMC on detection of any wake event initiates a stop message to the power accumulator device. Once an operating system (OS) context is restored, software can read the measured data from the power accumulator device. The measured data is accessible to a host software using standard software application programming interface (API) and can be used to influence the power policies of the system.

First claim

What is claimed is:

1. An apparatus comprising:
one or more channels to receive power supply lines;
an input to receive, in response to a processor being placed into a low power mode, instructions from a power management controller (PMC), wherein the instructions are to:
measure power on respective ones of the power supply lines; and
generate measured data related to measured power on the respective ones of the power supply lines while the processor is in the low power mode;

a memory to store the measured data; and
an input-output (I/O) interface to communicate with an operating system, wherein the operating system is to access the measured data.

2. The apparatus of claim 1 comprises an analog-to-digital converter (ADC) to convert voltage and/or current on the power supply lines to a digital representation, wherein the measured data corresponds to the digital representation.

3. The apparatus of claim 1 , wherein the operating system is to initiate the low power mode to the PMC.

4. The apparatus of claim 1 , wherein the PMC is to cause stop of measurement of power in response to a wake event.

5. The apparatus of claim 1 , wherein the operating system includes an application programming interface (API) for an application to process the measured data.

6. The apparatus of claim 1 , wherein the one or more channels are coupled to one or more voltage regulators.

7. The apparatus of claim 1 , wherein the power management controller is part of a system-on-chip (SoC).

8. The apparatus of claim 1 , wherein the instructions include instructions to start power measurement and instructions to stop power measurement.

9. The apparatus of claim 1 , wherein the input is a general purpose I/O (GPIO) interface.

10. The apparatus of claim 1 , wherein the low power mode is an SOiX state.

11. An apparatus comprising:
a plurality of processor cores;
a power management controller (PMC) coupled to the plurality of processor cores, the PMC to:
manage power for the plurality of processor cores; and
cause the apparatus to enter a low power mode; and

a power accumulator, wherein the PMC is to cause the power accumulator, in response to a processor core of the plurality of processor cores being placed into a low power mode, to:
measure power drawn by the apparatus while the apparatus is in the low power mode; and
generate measured data related to the measured power.

12. The apparatus of claim 11 , wherein the PMC is to cause the power accumulator to stop measurement of power drawn by the apparatus when the apparatus exits the low power mode.

13. The apparatus of claim 11 , wherein the power accumulator is to provide an indication of the measured power to an operating system.

14. The apparatus of claim 13 , wherein the operating system includes an application programming interface (API) for an application to process the measured power.

15. The apparatus of claim 11 , wherein the low power mode is an S0iX state.

16. A system comprising:
a power accumulator;
a system-on-chip coupled to the power accumulator, wherein the system-on-chip comprises:
a plurality of processor cores;
a power management controller (PMC) coupled to the plurality of processor cores, the PMC to:
manage power for the plurality of processor cores; and
cause the system-on-chip to enter a low power mode; and

an output to communicate with the power accumulator, wherein the PMC is to cause the power accumulator, in response to a processor core of the plurality of processor cores being placed into a low power mode;
measure power drawn by the system-on-chip while the system-on-chip is in the low power mode; and
generate measured data related to the measured power; and

an input-output (TO) interface to communicate with an operating system, wherein the operating system is to access the measured data.

17. The system of claim 16 , wherein the power accumulator comprises an analog-to-digital converter (ADC) to convert voltage and/or current on power supply lines to a digital representation, wherein the power supply lines provide power to the system-on-chip, and wherein the measured data corresponds to the digital representation.

18. The system of claim 16 , wherein the operating system is to initiate the low power mode to the PMC.

Assignees

• Intel Corp

Inventors

• Ranganathan Sriram
• G Naveen
• Rajagopal Pannerkumar
• Gettimalli Govindaraj
• Ragothaman Javahar

Classifications

• G01R21/133 Primary

  by using digital technique · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G01R21/00 Primary

  Arrangements for measuring electric power or power factor (G01R7/12 takes precedence) · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G06F1/3246

  by software initiated power-off · CPC title