Transistor device with a varying gate runner resistivity per area

Patent metadata

Field	Value
Publication number	US-11417747-B2
Application number	US-202017072602-A
Country	US
Kind code	B2
Filing date	Oct 16, 2020
Priority date	Oct 17, 2019
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

In an example, a transistor device is provided. The transistor device includes a plurality of transistor cells each including a gate electrode and each at least partially integrated in a semiconductor body that includes a wide bandgap semiconductor material. The transistor device includes a gate pad arranged on top of the semiconductor body, and a plurality of gate runners each arranged on top of the semiconductor body and each connected to gate electrodes of at least some of the plurality of transistor cells. Each gate runner of the plurality of gate runners has a longitudinal direction, and at least one of the gate runners includes at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.

First claim

The invention claimed is:

1. A transistor device, comprising:
a plurality of transistor cells, wherein each transistor cell of the plurality of transistor cells comprises a gate electrode and each transistor cell of the plurality of transistor cells is at least partially integrated in a semiconductor body that comprises a wide bandgap semiconductor material;
a gate pad arranged on top of the semiconductor body; and
a plurality of gate runners, wherein each gate runner of the plurality of gate runners is arranged on top of the semiconductor body and each gate runner of the plurality of gate runners is connected to gate electrodes of at least some of the plurality of transistor cells, wherein:
each gate runner of the plurality of gate runners extends in a longitudinal direction, and
at least one gate runner of the plurality of gate runners comprises at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.

2. The transistor device of claim 1 ,
wherein each gate runner of the plurality of gate runners comprises at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.

3. The transistor device of claim 2 ,
wherein gate runners of the plurality of gate runners are essentially parallel to each other.

4. The transistor device of claim 1 ,
wherein the at least a section in which the resistivity per area increases is implemented such that a cross sectional area of the at least a section decreases in the longitudinal direction.

5. The transistor device of claim 4 ,
wherein the at least a section comprises an essentially constant height and wherein a width of the at least a section decreases in the longitudinal direction.

6. The transistor device of claim 4 ,
wherein the at least a section comprises an essentially constant width and wherein a height of the at least a section decreases in the longitudinal direction.

7. The transistor device of claim 1 ,
wherein the at least a section in which the resistivity per area increases is implemented such that a resistivity of the at least one gate runner increases in the longitudinal direction.

8. The transistor device of claim 1 ,
wherein a ratio between a maximum resistivity per area and a minimum resistivity per area of the at least one gate runner is at least 2.

9. The transistor device of claim 1 , comprising:
at least one connection runner connected between the gate pad and at least some of the plurality of gate runners.

10. The transistor device of claim 1 ,
wherein each transistor cell of the plurality of transistor cells comprises:
a drift region, a source region, and a body region, wherein the body region is arranged between the source region and the drift region and the body region is dielectrically insulated from the gate electrode by a gate dielectric.

11. The transistor device of claim 1 ,
wherein gate electrodes of one or more transistor cells of the plurality of transistor cells are formed by a respective elongated trench electrode of a plurality of elongated trench electrodes.

12. The transistor device of claim 11 ,
wherein elongated trench electrodes of the plurality of elongated trench electrodes are essentially perpendicular to gate runners of the plurality of gate runners.

13. The transistor device of claim 11 ,
wherein angles between elongated trench electrodes of the plurality of elongated trench electrodes and gate runners of the plurality of gate runners are between 30° and 60°.

14. The transistor device of claim 11 ,
wherein each gate runner of the plurality of gate runners crosses elongated trench electrodes of the plurality of elongated trench electrodes, and
wherein each gate runner of the plurality of gate runners is connected to each elongated trench electrode that the gate runner crosses.

15. The transistor device of claim 11 ,
wherein each gate runner of the plurality of gate runners crosses elongated trench electrodes of the plurality of elongated trench electrodes, and
wherein each gate runner of the plurality of gate runners is connected to less than every elongated trench electrode that the gate runner crosses.

16. The transistor device of claim 1 , wherein the wide bandgap semiconductor material is silicon carbide.

17. A transistor device, comprising:
a plurality of transistor cells, wherein each transistor cell of the plurality of transistor cells comprises a gate electrode and each transistor cell of the plurality of transistor cells is at least partially integrated in a semiconductor body that comprises a wide bandgap semiconductor material;
a gate pad arranged on top of the semiconductor body; and
a plurality of gate runners, wherein each gate runner of the plurality of gate runners is arranged on top of the semiconductor body and each gate runner of the plurality of gate runners is connected to gate electrodes of at least some of the plurality of transistor cells, wherein:
each gate runner of the plurality of gate runners has a longitudinal direction,
each gate runner of the plurality of gate runners comprises at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases, and
a ratio between a maximum resistivity per area and a minimum resistivity per area of a gate runner of the plurality of gate runners is at least 2.

18. The transistor device of claim 17 , wherein the wide bandgap semiconductor material is silicon carbide.

19. A transistor device, comprising:
a plurality of transistor cells, wherein each transistor cell of the plurality of transistor cells comprises a gate electrode and each transistor cell of the plurality of transistor cells is at least partially integrated in a semiconductor body that comprises a wide bandgap semiconductor material;
a gate pad arranged on top of the semiconductor body;
a plurality of gate runners, wherein each gate runner of the plurality of gate runners is arranged on top of the semiconductor body and each gate runner of the plurality of gate runners is connected to gate electrodes of at least some of the plurality of transistor cells, and
at least one connection runner connected between the gate pad and at least some of the plurality of gate runners, wherein:
each gate runner of the plurality of gate runners extends in a longitudinal direction, and
each gate runner of the plurality of gate runners comprises at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.

20. The transistor device of claim 19 , wherein the wide bandgap semiconductor material is silicon carbide.

Assignees

• Infineon Technologies Ag

Inventors

• Aichinger Thomas
• Bergner Wolfgang
• Siemieniec Ralf
• Wolter Frank

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title