Memory device having electrically floating body transistor

Patent metadata

Field	Value
Publication number	US-11417657-B2
Application number	US-202117207687-A
Country	US
Kind code	B2
Filing date	Mar 21, 2021
Priority date	Apr 8, 2012
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

First claim

That which is claimed is:

1. A semiconductor memory cell comprising:
a first bipolar device having a first floating base region, a first collector, and a first emitter, and
a second bipolar device having a second floating base region, a second collector, and a second emitter,
wherein said first floating base region is common to said second floating base region,
wherein said first collector is common to said second collector,
wherein a state of said memory cell is maintained through a back bias applied to said first and second collectors;
wherein said first and second collectors are commonly connected to at least two of said memory cells; and
wherein said first and second collector regions have a band gap that is lower than a band gap of said first and second floating base regions.

2. The semiconductor memory cell of claim 1 , further comprising a gate region positioned above said first and second floating base regions.

3. The semiconductor memory cell of claim 1 , wherein said first and second collectors are configured to maintain a charge in said floating base regions.

4. The semiconductor memory cell of claim 1 , wherein said state of said memory cell is a state selected from at least first and second states, and wherein said first and second states are stable states.

5. The semiconductor memory cell of claim 1 , wherein said state of said memory cell is a state selected from at least first and second states; and wherein a product of forward emitter gain and impact ionization efficiency of said first and second bipolar transistors approaches unity when said memory cell is in one of said first and second states, and wherein impact ionization, when said memory cell is in the other of said first and second states is less than the impact ionization when said memory cell is in said one of said first and second states.

6. The semiconductor memory cell of claim 1 , wherein said state of said memory cell is maintained through impact ionization.

7. The semiconductor memory cell of claim 1 , wherein at least a portion of said semiconductor memory cell is formed in a fin structure.

8. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes: a first bipolar device having a first floating base region, a first collector, and a first emitter, and a second bipolar device having a second floating base region, a second collector, and a second emitter;
wherein said first floating base region is common to said second floating base region;
wherein said first collector is common to said second collector; wherein a state of said memory cell is maintained through a back bias applied to said first and second collectors; wherein said first and second collectors are commonly connected to at least two of said memory cells; and wherein said first and second collectors have a band gap that is lower than a band gap of said first and second floating base regions.

9. The semiconductor memory array of claim 8 , wherein each of said semiconductor memory cells further comprises a gate region positioned above said first and second floating base regions, respectively.

10. The semiconductor memory array of claim 8 , wherein said first and second collectors are configured to maintain a charge in said floating base regions.

11. The semiconductor memory array of claim 8 , wherein said state of said memory is selected from at least first and second states; and wherein said first and second states are stable states.

12. The semiconductor memory array of claim 8 , wherein said state of said memory is selected from at least first and second states; wherein a product of forward emitter gain and impact ionization efficiency of said first and second bipolar transistors approaches unity when said memory cell is in one of said first and second states, and wherein impact ionization, when said memory cell is in the other of said first and second states is less than the impact ionization when said memory cell is in said one of said first and second states.

13. The semiconductor memory array of claim 8 , wherein said memory cell states are maintained through impact ionization.

14. The semiconductor memory array of claim 8 , wherein at least a portion of each said semiconductor memory cell is formed in at least one fin structure, respectively.

15. An integrated circuit comprising: a semiconductor memory array comprising: a plurality of semiconductor memory cells arranged in a matrix of rows and columns,
wherein each said semiconductor memory cell includes:
a first bipolar device having a first floating base region, a first collector, and a first emitter; and
a second bipolar device having a second floating base region, a second collector, and a second emitter;
wherein said first floating base region is common to said second floating base region;
wherein said first collector is common to said second collector;
wherein a state of said memory cell is maintained through a back bias applied to said first and second collectors;
wherein said first and second collectors are commonly connected to at least two of said memory cells;
wherein said first and second collectors have a band gap that is lower than a band gap of said first and second floating base regions;
and
a control circuit configured to provide electrical signals to apply said back bias.

16. The integrated circuit of claim 15 , wherein each of said semiconductor memory cells further comprises a gate region positioned above said first and second floating base regions, respectively.

17. The integrated circuit of claim 15 , wherein said first and second collectors are configured to maintain a charge in said floating base regions.

18. The integrated circuit of claim 15 , wherein said state of said memory cell is selected from at least first and second states; and wherein said first and second states are stable states.

19. The integrated circuit of claim 15 , wherein said memory cell states are maintained through impact ionization.

20. The integrated circuit of claim 15 , wherein at least a portion of at least one of said semiconductor memory cells is formed in a fin structure.

Assignees

• Zeno Semiconductor Inc

Inventors

• Widjaja Yuniarto
• Han Jin-Woo
• Louie Benjamin S

Classifications

• H10D62/177

  Base regions of bipolar transistors, e.g. BJTs or IGBTs · CPC title

• H10D10/40

  Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)} · CPC title

• H10D84/121

  BJTs having built-in components · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/137

  Collector regions of BJTs · CPC title