Semiconductor structure having a semiconducture substrate and an isolation component

Patent metadata

Field	Value
Publication number	US-11417647-B2
Application number	US-201916535391-A
Country	US
Kind code	B2
Filing date	Aug 8, 2019
Priority date	Aug 17, 2018
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first region and the second region; an isolation component located in the isolation region; and where the isolation component is configured to recombine first carriers flowing from the first region toward the second region, and to extract second carriers flowing from the second region toward the first region.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a) a P-type semiconductor substrate having a first region comprising an N-type first well region, a second region, and an isolation region disposed between the first region and the second region;
b) an isolation component located in the isolation region, wherein a portion of the isolation component that is adjacent to the semiconductor substrate is N-type doped, and an electric potential connected to the isolation component is higher than an electric potential of the semiconductor substrate;
c) wherein the isolation component is configured to recombine hole carriers flowing from the first region toward the second region, and to extract electron carriers flowing from the second region toward the first region;
d) wherein a first N-type MOSFET is disposed in the first well region and a second N-type MOSFET is disposed in the second region, and a parasitic PNP transistor is formed by a P-type body region of the first N-type MOSFET, the first well region, and the semiconductor substrate;
e) wherein a parasitic NPN transistor is formed by the first well region, the semiconductor substrate, and an N-type region of the second N-type MOSFET that is adjacent to the semiconductor substrate; and
f) wherein the hole carriers flow from the PNP transistor toward the second region when the PNP transistor is turned on, and the electron carriers flow from the NPN transistor toward the first region when the NPN transistor is turned on.

2. The semiconductor structure according to claim 1 , wherein:
a) the second region comprises an N-type second well region;
b) the second N-type MOSFET is disposed in the second well region; and
c) the N-type region is the second well region.

3. The semiconductor structure according to claim 1 , wherein:
a) a drain electrode of the first N-type MOSFET is connected to a first electric potential;
b) a source electrode of the first N-type MOSFET is coupled to a drain electrode of the second N-type MOSFET;
c) a drain electrode of the second N-type MOSFET is connected to a second electric potential; and
d) the first electric potential is greater than the second electric potential.

4. The semiconductor structure according to claim 2 , wherein:
a) the first N-type MOSFET is configured as a high-voltage side transistor of a first half-bridge circuit;
b) the second N-type MOSFET is configured as a low-voltage side transistor of a second half-bridge circuit; and
c) a source electrode of the first N-type MOSFET is coupled to a drain electrode of the second N-type MOSFET through an inductive element.

5. The semiconductor structure according to claim 1 , wherein a source region of the first N-type MOSFET is located in the P-type body region.

6. The semiconductor structure according to claim 3 , wherein the electric potential connected to the isolation component is the same as the first electric potential.

7. The semiconductor structure according to claim 1 , wherein the isolation component comprises:
a) at least one trench extending from a surface of the semiconductor substrate into the semiconductor substrate;
b) an N-type doped polysilicon filled in the trench; and
c) wherein a depth of the trench in the semiconductor substrate is greater than a depth of the first well region in the semiconductor substrate along a thickness direction of the semiconductor substrate.

8. The semiconductor structure according to claim 7 , wherein the isolation component further comprises an N-type contact region located in a surface of the isolation region and being in contact with the trench.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Du Yicheng
• Wang Meng
• Yu Hui

Classifications

• H10W10/031 Primary

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/0148

  comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers · CPC title