Integration of multiple discrete GaN devices

Patent metadata

Field	Value
Publication number	US-11417644-B2
Application number	US-202016903961-A
Country	US
Kind code	B2
Filing date	Jun 17, 2020
Priority date	Jun 17, 2020
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

Examples of integrated semiconductor devices are described. In one example, an integrated device includes first and second transistors formed on a substrate, where the transistors share a terminal metal feature to reduce a size of the integrated device. The terminal metal feature can include a shared source electrode metalization, for example, although other electrode metalizations can be shared. In other aspects, a first width of a gate of the first transistor can be greater than a second width of a gate of the second transistor, and the shared metalization can taper from the first width to the second width. The integrated device can also include a metal ground plane on a backside of the substrate, and the terminal metal feature can also include an in-source via for the shared source electrode metalization. The in-source via can electrically couple the shared source electrode metalization to the metal ground plane.

First claim

Therefore, the following is claimed:

1. An integrated semiconductor device, comprising:
a first transistor formed on a substrate; and
a second transistor formed on the substrate, wherein:
a first width of a gate finger of the first transistor is greater than a second width of a gate finger of the second transistor;
the first transistor and the second transistor share at least one terminal metal feature to reduce a size of the integrated semiconductor device; and
the at least one terminal metal feature is positioned between the gate finger of the first transistor and the gate finger of the second transistor.

2. The integrated semiconductor device of claim 1 , wherein the at least one terminal metal feature comprises a shared source electrode metalization of the first transistor and the second transistor.

3. The integrated semiconductor device of claim 2 , wherein:
the shared source electrode metalization comprises at least one metalization taper from a size of the first width to a size of the second width.

4. The integrated semiconductor device of claim 2 , further comprising:
a metal layer ground plane on a backside of the substrate, wherein:
the at least one terminal metal feature further comprises an in-source via for the shared source electrode metalization; and
the in-source via electrically couples the shared source electrode metalization of the first transistor and the second transistor to the metal layer ground plane.

5. The integrated semiconductor device of claim 1 , wherein:
the first transistor comprises a number of gate fingers, a number of drain electrodes, and a number of source electrodes;
the gate fingers, drain electrodes, and source electrodes are interdigitated among each other; and
each drain electrode among the number of drain electrodes is positioned between two gate fingers among the number of gate fingers.

6. The integrated semiconductor device of claim 1 , wherein a gate-to-gate pitch of the first transistor is smaller than the gate-to-gate pitch of the second transistor.

7. The integrated semiconductor device of claim 1 , wherein the first transistor and the second transistor comprise power transistors in an amplifier.

8. The integrated semiconductor device of claim 1 , wherein:
the first transistor comprises a main power transistor in a Doherty amplifier; and
the second transistor comprises a peak power transistor in the Doherty amplifier.

9. The integrated semiconductor device of claim 1 , wherein the substrate comprises at least one of silicon or silicon carbide.

10. The integrated semiconductor device of claim 9 , further comprising:
a gallium nitride semiconductor material layer formed over the substrate.

11. The integrated semiconductor device of claim 1 , wherein the first transistor and the second transistor comprise gallium nitride semiconductor material power transistors.

12. An integrated semiconductor device, comprising:
a first active device formed on a substrate; and
a second active device formed on the substrate, wherein:
a first width of an electrode of the first active device is greater than a second width of an electrode of the second active device;
the first active device and the second active device share at least one terminal metal feature to reduce a size of the integrated semiconductor device; and
the at least one terminal metal feature is positioned between the electrode of the first active device and the electrode of the second active device.

13. The integrated semiconductor device of claim 12 , wherein the at least one terminal metal feature comprises a shared electrode metalization of the first active device and the second active device.

14. The integrated semiconductor device of claim 13 , wherein:
the shared electrode metalization comprises at least one metalization taper from a size of the first width to a size of the second width.

15. The integrated semiconductor device of claim 13 , further comprising:
a metal layer ground plane on a backside of the substrate, wherein:
the at least one terminal metal feature further comprises an in-electrode via for the shared electrode metalization; and
the in-electrode via electrically couples the shared electrode metalization of the first active device and the second active device to the metal layer ground plane.

16. The integrated semiconductor device of claim 12 , wherein:
the first active device comprises a number of gate fingers, a number of drain electrodes, and a number of source electrodes;
the gate fingers, drain electrodes, and source electrodes are interdigitated among each other; and
each drain electrode among the number of drain electrodes is positioned between two gate fingers among the number of gate fingers.

17. The integrated semiconductor device of claim 12 , wherein a gate-to-gate pitch of the first active device is smaller than the gate-to-gate pitch of the second active device.

18. The integrated semiconductor device of claim 12 , wherein:
the first active device comprises a main power transistor in a Doherty amplifier; and
the second active device comprises a peak power transistor in the Doherty amplifier.

19. The integrated semiconductor device of claim 12 , wherein the substrate comprises at least one of silicon or silicon-carbide.

20. The integrated semiconductor device of claim 12 , wherein the first active device and the second active device comprise gallium nitride semiconductor material power transistors.

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Som Shamit
• Atherton John Stephen
• Struble Wayne Mack
• Barrett Jason Matthew
• Yamujala Nishant R

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W20/484

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title