Flip-chip device

Patent metadata

Field	Value
Publication number	US-11417622-B2
Application number	US-202017071432-A
Country	US
Kind code	B2
Filing date	Oct 15, 2020
Priority date	Oct 18, 2019
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.

First claim

What is claimed is:

1. An apparatus including a flip-chip device, the flip-chip device comprising:
a die having a plurality of under bump metallizations (UBMs);
a package substrate having a plurality of bond pads; and
a plurality of solder joints coupling the die to the package substrate, wherein the plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, the plurality of solder bumps being directly connected to the plurality of bond pads,
wherein the flip-chip device has a bond line thickness to solder joint diameter ratio of less than one, the bond line thickness being a distance between the die and the package substrate.

2. The flip-chip device of claim 1 , wherein the flip-chip device has the bond line thickness to solder joint diameter ratio of approximately 0.64.

3. The flip-chip device of claim 2 , wherein the bond line thickness is approximately 35 um.

4. The flip-chip device of claim 2 , wherein a solder joint diameter for each of the plurality of solder joints is approximately 95 um.

5. The flip-chip device of claim 1 , further comprising:
a solder resist layer, of the package substrate, having a solder resist opening (SRO) over each bond pad of the plurality of bond pads, wherein a ratio of SRO to solder joint diameter is approximately 0.95.

6. The flip-chip device of claim 5 , wherein the SRO over each bond pad is approximately 35 um.

7. The flip-chip device of claim 5 , wherein the solder joint diameter for each of the plurality of solder joints is approximately 95 um.

8. The flip-chip device of claim 1 , wherein the flip-chip device has the bond line thickness to solder joint diameter ratio in a range of approximately 0.3 to 0.7.

9. The flip-chip device of claim 8 , wherein the bond line thickness is in a range of approximately 30 um to 60 um.

10. The flip-chip device of claim 8 , wherein a solder joint diameter for each of the plurality of solder joints is in a range of approximately 70 um to 180 um.

11. The flip-chip device of claim 1 , wherein the plurality of solder joints, each has a generally cylindrical or columnar shape.

12. The flip-chip device of claim 1 , wherein the plurality of bond pads are formed of copper.

13. The flip-chip device of claim 1 , wherein each UBM, of the plurality of UBMs, has a minimum metal density and a minimum via density in an area under each UBM.

14. The flip-chip device of claim 13 , wherein the minimum metal density is 20 percent.

15. The flip-chip device of claim 13 , wherein the minimum via density is 0.1 percent.

16. The flip-chip device of claim 13 , wherein the area under the UBM is divided into a plurality of checking windows to check the minimum metal density and the minimum via density.

17. The flip-chip device of claim 16 , wherein each checking window is in a range of 5 um by 5 um to 20 um by 20 um.

18. The apparatus of claim 1 , wherein the apparatus is selected from a group comprising at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, or a device in an automotive vehicle.

19. A method for manufacturing a flip-chip device, the method comprising:
providing a die having a plurality of solder bumps plated on a plurality of under bump metallizations (UBMs);
providing a package substrate having a plurality of bond pads; and
forming a plurality of solder joints coupling the die to the package substrate, wherein the plurality of solder joints are formed from the plurality of solder bumps being directly connected to the plurality of bond pads during a reflow process,
wherein the flip-chip device has a bond line thickness to solder joint diameter ratio of less than one, the bond line thickness being a distance between the die and the package substrate.

20. The method of claim 19 , wherein the flip-chip device has the bond line thickness to solder joint diameter ratio of approximately 0.64.

21. The method of claim 20 , wherein the bond line thickness is approximately 35 um.

22. The method of claim 20 , wherein a solder joint diameter for each of the plurality of solder joints is approximately 95 um.

23. The method of claim 19 , wherein the package substrate includes a solder resist layer having a solder resist opening (SRO) over each bond pad of the plurality of bond pads and wherein a ratio of SRO to solder joint diameter is approximately 0.95.

24. The method of claim 23 , wherein the SRO over each bond pad is approximately 35 um.

25. The method of claim 23 , wherein the solder joint diameter for each of the plurality of solder joints is approximately 95 um.

26. The method of claim 19 , further comprising:
checking a minimum metal density and a minimum via density in an area under each UBM of the plurality of UBMs.

27. The method of claim 26 , wherein the minimum metal density is 20 percent.

28. The method of claim 26 , wherein the minimum via density is 0.1 percent.

29. The method of claim 26 , wherein the area under the UBM is divided into a plurality of checking windows to check the minimum metal density and the minimum via density.

30. The method of claim 29 , wherein each checking window is in a range of 5 um by 5 um to 20 um by 20 um.

Assignees

• Qualcomm Inc

Inventors

• Sun Yangyang
• Holmes John
• Zhang Xuefeng
• He Dongming

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/221

  Structures or relative sizes · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title