Laser component and method of producing same
US-10511138-B2 · Dec 17, 2019 · US
Package structure
US11417581B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11417581-B2 |
| Application number | US-201815997845-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 5, 2018 |
| Priority date | Nov 10, 2014 |
| Publication date | Aug 16, 2022 |
| Grant date | Aug 16, 2022 |
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- Title
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- Abstract
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- Assignees and inventors
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- Key dates
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- First independent claim
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- CPC / IPC classifications
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- Citations and related patents
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Abstract
Official abstract text for this publication.
A semiconductor package is provided and includes: an insulative layer having opposing first and second surfaces; a wiring layer embedded in the insulative layer and having a first side that is exposed from the first surface of the insulative layer and a second side opposing the first side and attached to the second surface of the insulative layer; at least one electronic component mounted on the second side of the wiring layer and electrically connected to the wiring layer; and an encapsulating layer formed on the second side of the wiring layer and the second surface of the insulative layer and encapsulating the electronic component. Therefore, the single wiring layer is allowed to be connected to the electronic component on one side and connected to solder balls on the other side thereof to shorten the signal transmission path.
First claim
Opening claim text (preview).
What is claimed is: 1. A package structure, comprising: a single insulative layer having opposing first and second surfaces; a wiring layer embedded in the single insulative layer and having a first side that is exposed from the first surface of the single insulative layer and a second side opposing the first side and attached to the second surface of the single insulative layer, wherein the second side of the wiring layer comprises a plurality of conductive traces, the conductive traces are protruded from the second surface of the single insulative layer, the first side of the wiring layer is defined to have a plurality of conductive pads thereon, and the conductive pads are integrally formed with the conductive traces and exposed from the first surface of the single insulative layer, the first side of the wiring layer is recessed on the first surface of the single insulative layer and is bonded with a plurality of conductive elements, the wiring layer is formed by integrally etching a metal plate and has a T shape, and a horizontal side of the T-shaped wiring layer is a chip-placement side, and a vertical side of the T-shaped wiring layer is a ball-placement side; at least one electronic component mounted on the conductive traces of the second side of the wiring layer and electrically connected to the conductive traces; and an encapsulating layer formed on the second side of the wiring layer and the second surface of the single insulative layer and encapsulating the electronic component, wherein the wiring layer is covered by the encapsulating layer and supported by the single insulative layer. 2. The package structure of claim 1 , wherein the second side of the wiring layer is electrically connected to the electronic component. 3. The package structure of claim 1 , wherein the electronic component is an active component, a passive component, or a combination thereof. 4. The package structure of claim 1 , wherein the electronic component is electrically connected to the wiring layer in a flip-chip manner. 5. The package structure of claim 1 , wherein the plurality of conductive elements are formed on the conductive pads and electrically connected to the first side of the wiring layer.
Assignees
Inventors
Classifications
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
characterised by the relative positions of pads or connectors relative to package parts · CPC title
on active surfaces of flip-chip devices, e.g. underfills · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US11417581B2 cover?
- A semiconductor package is provided and includes: an insulative layer having opposing first and second surfaces; a wiring layer embedded in the insulative layer and having a first side that is exposed from the first surface of the insulative layer and a second side opposing the first side and attached to the second surface of the insulative layer; at least one electronic component mounted on th…
- Who is the assignee on this patent?
- Phoenix Pioneer Technology Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W74/117. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 16 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).