Asymmetric pass field-effect transistor for non-volatile memory
US-2020020402-A1 · Jan 16, 2020 · US
Non-volatile memory device and control method for mitigating memory cell overwritten
US11417397B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11417397-B2 |
| Application number | US-202016988729-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 10, 2020 |
| Priority date | May 6, 2020 |
| Publication date | Aug 16, 2022 |
| Grant date | Aug 16, 2022 |
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Abstract
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A control method of a non-volatile memory device is provided. The non-volatile memory device includes a memory array including a plurality of memory strings. Each memory string includes a plurality of memory cells connected in series. The control method includes applying a pass voltage signal to a plurality of unselected word lines connected to unselected memory cells of the plurality of memory cells during a programming operation period; and applying a program voltage signal to a selected word line connected to a selected memory cell of the plurality of memory cells during the programming operation period, wherein the program voltage signal is decreasing or changes in a descending step pulse manner during the programming operation period.
First claim
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What is claimed is: 1. A control method of a non-volatile memory device, the non-volatile memory device comprising a memory array comprising a plurality of memory strings, each memory string comprising a plurality of memory cells connected in series, the control method comprising: applying a pass voltage signal to a plurality of unselected word lines connected to unselected memory cells of the plurality of memory cells during a programming operation period; and applying a program voltage signal to a selected word line connected to a selected memory cell of the plurality of memory cells during the programming operation period, wherein the program voltage signal is decreasing or changes in a descending step pulse manner during the programming operation period comprising a first period, a second period and a third period occurring consecutively and a voltage level of the program voltage signal in the second period of the programming operation period is set to be a normal program voltage, wherein the step comprising: applying the program voltage signal having a voltage level greater than the normal program voltage to the selected word line in the first period for performing an over driving scheme on the selected word line; applying the program voltage signal set to the normal program voltage to the selected word line in the second period; and applying the program voltage signal having a voltage level smaller than the normal program voltage to the selected word line in the third period for providing compensation. 2. The control method of claim 1 , wherein a voltage level of the program voltage signal is greater than a voltage level of the pass voltage signal. 3. The control method of claim 1 , wherein the non-volatile memory device is an NAND flash memory. 4. A non-volatile memory device, comprising: a memory array comprising a plurality of memory strings, each memory string comprising a plurality of memory cells connected in series; a plurality of word lines connected to the plurality of memory cells of the each memory string of the plurality of memory strings, each word line connected to a respective memory cell; and a control circuit configured to apply a pass voltage signal to unselected word lines of the plurality of word lines connected to unselected memory cells of the plurality of memory cells during a programming operation period and apply a program voltage signal to a selected word line of the plurality of word lines connected to a selected memory cell of the plurality of memory cells during the programming operation period, wherein the program voltage signal is decreasing or changes in a descending step pulse manner during the programming operation period comprising a first period, a second period and a third period occurring consecutively and a voltage level of the program voltage signal in the second period of the programming operation period is set to be a normal program voltage, wherein the control circuit is configured to apply the program voltage signal having a voltage level greater than the normal program voltage to the selected word line in the first period for performing an over driving scheme on the selected word line, apply the program voltage signal set to the normal program voltage to the selected word line in the second period, and apply the program voltage signal having a voltage level smaller than the normal program voltage to the selected word line in the third period for providing compensation. 5. The non-volatile memory device of claim 4 , wherein a voltage level of the program voltage signal is greater than a voltage level of the pass voltage signal. 6. The non-volatile memory device of claim 4 , wherein the non-volatile memory device is an NAND flash memory.
Assignees
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Classifications
Power supply circuits · CPC title
- G11C16/0483Primary
comprising cells having several storage transistors connected in series · CPC title
- G11C16/10Primary
Programming or data input circuits · CPC title
Address circuits; Decoders; Word-line control circuits · CPC title
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- What does patent US11417397B2 cover?
- A control method of a non-volatile memory device is provided. The non-volatile memory device includes a memory array including a plurality of memory strings. Each memory string includes a plurality of memory cells connected in series. The control method includes applying a pass voltage signal to a plurality of unselected word lines connected to unselected memory cells of the plurality of memory…
- Who is the assignee on this patent?
- Yangtze Memory Tech Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G11C16/0483. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 16 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).