Nonvolatile memory device and a method of operating the nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-9653168-B2
Application number	US-201615010529-A
Country	US
Kind code	B2
Filing date	Jan 29, 2016
Priority date	Feb 3, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A method of programming a nonvolatile memory device includes: applying a first voltage to a first wordline of the nonvolatile memory device; and applying a second voltage to a second wordline of the nonvolatile memory device, wherein the second voltage is greater than the first voltage; decreasing the first voltage; decreasing the second voltage, wherein a difference between the first voltage and the second voltage is maintained for a predetermined time; and discharging the second voltage.

First claim

What is claimed is:

1. A method of programming a nonvolatile memory device, comprising:
applying a first voltage to a first wordline of the nonvolatile memory device, wherein the first wordline is connected to a first memory cell; and
applying a second voltage to a second wordline of the nonvolatile memory device, wherein the second voltage is greater than the first voltage, wherein the second wordline is connected to a second memory cell;
decreasing the first voltage;
decreasing the second voltage, wherein a difference between the first voltage and the second voltage is maintained for a predetermined time; and
discharging the second voltage.

2. The method of claim 1 , wherein the first voltage is a pass voltage and the second voltage is a program voltage.

3. The method of claim 2 , wherein the first wordline is an unselected wordline, and the second wordline is a selected wordline.

4. The method of claim 1 , Wherein the first voltage starts being decreased after the second voltage starts being decreased.

5. The method of claim 1 , wherein the second voltage stops being decreased before the first voltage starts being decreased.

6. The method of claim 1 , wherein decreasing the second voltage comprises decreasing the second voltage to a first level, and then, decreasing the second voltage to a second level lower than the first level.

7. The method of claim 1 , wherein decreasing the first voltage comprises decreasing the first voltage to a first level, and then, decreasing the first voltage to a second level lower than the first level.

8. The method of claim 1 , Wherein a program operation comprises the steps of applying the first voltage, applying the second voltage, decreasing the first voltage, decreasing the second voltage and discharging the second voltage, the method further comprising:
performing a verification operation of the program operation;
determining whether the verification operation passes or fails; and
repeating the program operation when the verification operation fails,
wherein, in repeating the program operation, the difference between the first voltage and the second voltage is changed, or
wherein, in repeating the program operation, the predetermined time is changed.

9. The method of claim 8 , wherein, in repeating the program operation, the difference between the first voltage and the second voltage is increased, or
wherein, in repeating the program operation, the predetermined time is increased.

10. The method of claim 1 , wherein a program operation comprises the steps of applying the first voltage, applying the second voltage, decreasing the first voltage, decreasing the second voltage and discharging the second voltage, wherein the program operation is performed after a target program state of a plurality of program states is program passed.

11. The method of claim 1 , wherein the difference between the first voltage and the second voltage depends on a location of the second wordline in a cell string, or
wherein the predetermined time depends on the location of the second wordline in the cell string.

12. The method of claim 1 , wherein the difference between the first voltage and the second voltage depends on a wordline group in which the second wordline is located in a cell string, or
wherein the predetermined time depends on the wordline group in which the second wordline is located in the cell string.

13. The method of claim 1 , wherein the nonvolatile memory device includes a cell string, the cell string including a plurality of memory cells, a first memory cell being connected to the first wordline and receiving the first voltage, a second memory cell being connected to the second wordline and receiving the second voltage.

14. The method of claim 13 , wherein the first and second memory cells are charge trap cells.

15. A method of programming a nonvolatile memory device, comprising:
applying a first voltage to a first wordline of the nonvolatile memory device, wherein the first wordline is connected to a first memory cell; and
applying a second voltage to a second wordline of the nonvolatile memory device, wherein the second voltage is greater than the first voltage, wherein the second wordline is connected to a second memory cell;
decreasing the first voltage;
decreasing the second voltage, wherein the second voltage is higher than the first voltage for a predetermined time; and
discharging the second voltage after the predetermined time.

16. The method of claim 15 , wherein the first voltage is a pass voltage, and the second voltage is a program voltage.

17. The method of claim 15 , wherein the predetermined time is about 10 μs.

18. The method of claim 15 , wherein the nonvolatile memory device includes a cell string, the cell string including a plurality of memory cells, a first memory cell being connected to the first wordline and receiving the first voltage, a second memory cell being connected to the second wordline and receiving the second voltage.

19. The method of claim 18 , wherein the first and second memory cells are charge trap cells.

20. A method for programming a NAND flash memory including a memory cell array, the memory cell array including a plurality of memory blocks, each block including a plurality of cell strings, each cell sting including a ground selection transistor, a plurality of cell transistors, and a string selection transistor sequentially stacked in a direction perpendicular to a surface of a substrate on which the cell string is disposed, the method comprising:
applying a first voltage to a first wordline of a cell string, Wherein the first voltage has a first level, wherein the first wordline is connected to a first memory cell;
applying a second voltage to a second wordline of the cell string, wherein the second voltage has a second level, wherein the second level is greater than the first level, wherein the second wordline is connected to a second memory cell;
decreasing the first voltage to a third level, wherein the third level is less than the first level;
decreasing the second voltage to a fourth level, Wherein the fourth level is less than the second level and greater than the third level, wherein a difference between the third level and the fourth level is constant for a predetermined time; and
discharging the second voltage to the third level.

21. The method of claim 20 , wherein the cell transistors are charge trap transistors.

22. The method of claim 20 , wherein the first voltage is a pass voltage, and the second voltage is a program voltage.

23. The method of claim 20 , wherein the third level has a range from 0V to 1.5V.

24. The method of claim 20 , further comprising:
applying a select voltage to a bitline of the cell string.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Wandong

Classifications

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title