Dot product multiplier mechanism

Patent metadata

Field	Value
Publication number	US-11416580-B2
Application number	US-201916682225-A
Country	US
Kind code	B2
Filing date	Nov 13, 2019
Priority date	Nov 13, 2019
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

An apparatus to facilitate matrix multiplication operations. The apparatus comprises multiplication hardware to operate in a dot product mode, wherein a multiplication stage included in the multiplication hardware is configured as a dot product of a number of bit vectors (N) to perform N×N multiplication operations on a plurality of multiplicands and perform addition operations on results of the N×N multiplication operations.

First claim

What is claimed is:

1. An apparatus to facilitate matrix multiplication operations, comprising:
multiplication hardware to operate in a dot product mode, wherein a multiplication stage included in the multiplication hardware is configured as a dot product of a number of bit vectors (N) to perform N×N multiplication operations, perform addition operations on results of the N×N multiplication operations and perform a swap of most significant bits and least significant bits of a first of a plurality of multiplicands prior to performing the multiplication operations.

2. The apparatus of claim 1 , wherein the multiplication stage reduces first and last terms of the multiplication operation to zero.

3. The apparatus of claim 2 , wherein the multiplication hardware further comprises an addition stage to perform an addition operation on middle terms of the multiplication operation.

4. The apparatus of claim 1 , wherein the multiplication hardware is further configured to operate in a conventional mode to perform 2N matrix multiply add operations.

5. The apparatus of claim 4 , wherein the multiplication hardware receives input and separates the input into a plurality of elements.

6. The apparatus of claim 5 , wherein the multiplication hardware determines whether to operate in the conventional mode or the dot product mode.

7. A method to facilitate matrix multiplication operations comprising operating multiplication hardware in a dot product mode, including:
configuring a multiplication stage as a dot product of a number of bit vectors (N) to perform N×N multiplication operations;
performing addition operations on results of the N×N multiplication operations; and
performing a swap of most significant bits and least significant bits of a first of a plurality of multiplicands prior to performing the multiplication operations.

8. The method of claim 7 , further comprising reducing first and last terms of the multiplication operation to zero.

9. The method of claim 8 , further comprising performing an addition operation on middle terms of the multiplication operation at an addition stage of the multiplication hardware.

10. The method of claim 7 , further comprising configuring the multiplication hardware to operate in a conventional mode to perform 2N matrix multiply add operations.

11. The method of claim 10 , further comprising:
receiving input at the multiplication hardware; and
separating the input into a plurality of elements.

12. The method of claim 11 , further comprising the multiplication hardware determines whether to operate in the conventional mode or the dot product mode.

13. A hardware accelerator comprising:
a systolic array, including multiplication hardware to operate in a dot product mode, wherein a multiplication stage included in the multiplication hardware is configured as a dot product of a number of bit vectors (N) to perform N×N multiplication operations, perform addition operations on results of the N×N multiplication operations and perform a swap of most significant bits and least significant bits of a first of a plurality of multiplicands prior to performing the multiplication operations.

14. The accelerator of claim 13 , wherein the multiplication stage reduces first and last terms of the multiplication operation to zero.

15. The accelerator of claim 14 , wherein the multiplication hardware further comprises an addition stage to perform an addition operation on middle terms of the multiplication operation.

16. The accelerator of claim 13 , wherein the multiplication hardware is further configured to operate in a conventional mode to perform 2N matrix multiply add operations.

17. The accelerator of claim 16 , wherein the multiplication hardware determines whether to operate in the conventional mode or the dot product mode.

Assignees

• Intel Corp

Inventors

• Mathew Nevin
• Marwaha Shubra
• Garg Ashutosh

Classifications

• G06N3/044

  Recurrent networks, e.g. Hopfield networks · CPC title

• G06N3/045

  Combinations of networks · CPC title

• G06N3/09

  Supervised learning · CPC title

• G06N3/098

  Distributed learning, e.g. federated learning · CPC title

• G06N3/0442

  characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] · CPC title