Deep trench integration processes and devices

Patent metadata

Field	Value
Publication number	US-11410873-B2
Application number	US-202016953567-A
Country	US
Kind code	B2
Filing date	Nov 20, 2020
Priority date	Nov 20, 2020
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.

First claim

The invention claimed is:

1. A method of forming a semiconductor device, the method comprising:
etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate, wherein the trench is characterized by a first width through the first depth;
forming a liner along sidewalls of the trench;
etching the trench to a second depth at least ten times greater than the first depth, wherein the trench is characterized by a second width through the second depth; and
filling the trench with a dielectric material, wherein a seam formed in the dielectric material is maintained below the first depth.

2. The method of forming a semiconductor device of claim 1 , further comprising:
patterning a hardmask overlying the semiconductor substrate to produce a recess characterized by the first width across the first surface of the semiconductor substrate.

3. The method of forming a semiconductor device of claim 1 , further comprising:
performing a chemical-mechanical polishing operation to remove the dielectric material from the first surface of the semiconductor substrate.

4. The method of forming a semiconductor device of claim 3 , wherein the seam is not exposed during the chemical-mechanical polishing operation.

5. The method of forming a semiconductor device of claim 1 , wherein the semiconductor substrate comprises silicon.

6. The method of forming a semiconductor device of claim 1 , wherein the dielectric material comprises silicon oxide.

7. The method of forming a semiconductor device of claim 1 , wherein the liner is formed conformally along exposed portions of the semiconductor substrate, the method further comprising:
etching the liner from a base of the trench at the first depth.

8. The method of forming a semiconductor device of claim 1 , wherein the first width is less than or about 40% greater than the second width.

9. The method of forming a semiconductor device of claim 1 , wherein the first depth is less than or about 10% of a depth through the trench from the first surface of the semiconductor substrate to a base of the trench at the second depth.

10. A method of forming a semiconductor device, the method comprising:
patterning an opening in a mask material overlying a first surface of a semiconductor substrate;
etching a trench from the first surface of the semiconductor substrate to a first depth within the semiconductor substrate, wherein the trench is characterized by a first width through the first depth;
forming a liner across the semiconductor substrate and mask material, including along sidewalls of the trench;
performing an anisotropic removal of the liner;
etching the trench to a second depth, wherein the trench is characterized by a second width through the second depth; and
filling the trench with a dielectric material, wherein a seam formed in the dielectric material is maintained below the first depth.

11. The method of forming a semiconductor device of claim 10 , wherein the liner is characterized by a thickness that is half a difference between the first width and the second width.

12. The method of forming a semiconductor device of claim 10 , further comprising:
performing a chemical-mechanical polishing operation to remove the dielectric material from the first surface of the semiconductor substrate.

13. The method of forming a semiconductor device of claim 12 , wherein the seam is not exposed during the chemical-mechanical polishing operation.

14. The method of forming a semiconductor device of claim 10 , wherein the semiconductor substrate comprises silicon.

15. The method of forming a semiconductor device of claim 10 , wherein the dielectric material comprises silicon oxide.

16. The method of forming a semiconductor device of claim 10 , wherein the trench is characterized by a depth-to-width aspect ratio of greater than or about 30.

17. The method of forming a semiconductor device of claim 10 , wherein the first width is less than or about 40% greater than the second width.

18. The method of forming a semiconductor device of claim 10 , wherein the first depth is less than or about 10% of a depth through the trench from the first surface of the semiconductor substrate to a base of the trench at the second depth.

19. A method of forming a semiconductor device, the method comprising:
etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate, wherein the trench is characterized by a first width through the first depth;
forming a liner across the semiconductor substrate, including along sidewalls of the trench;
performing an anisotropic removal of the liner;
etching the trench to a second depth, wherein the trench is characterized by a second width through the second depth; and
filling the trench with a dielectric material, wherein a seam formed in the dielectric material is maintained below the first depth.

20. The method of forming a semiconductor device of claim 19 , further comprising:
performing a chemical-mechanical polishing operation to remove the dielectric material from the first surface of the semiconductor substrate, wherein the seam is not exposed during the chemical-mechanical polishing operation.

Assignees

• Applied Materials Inc

Inventors

• Yu Lan
• Sherwood Tyler
• Chudzik Michael
• Krishnan Siddarth

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/20

  Air gaps · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W20/081 Primary

  by forming openings in the dielectric parts · CPC title