Digital isolator

Patent metadata

Field	Value
Publication number	US-11405241-B2
Application number	US-202117318642-A
Country	US
Kind code	B2
Filing date	May 12, 2021
Priority date	Sep 18, 2019
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion.

First claim

What is claimed is:

1. A digital isolator, comprising:
a first metal portion;
a first insulating portion provided on the first metal portion;
a second metal portion provided on the first insulating portion;
a third metal portion including
a first portion provided around the first metal portion in a direction perpendicular to a first direction, the first direction being from the first metal portion toward the second metal portion;
a second portion provided on a portion of the first portion with a first conductive layer interposed;
a third portion provided on the second portion and provided around the second metal portion in the perpendicular direction; and

a first layer contacting the first conductive layer and an other portion of the first portion and being provided around a bottom portion of the second portion,
the first layer including silicon and carbon.

2. The isolator according to claim 1 , further comprising a first insulating layer provided between the first metal portion and the first insulating portion.

3. The isolator according to claim 2 , wherein
the first insulating layer contacts the first conductive layer and is provided also between the first insulating portion and the other portion of the first portion, and
at least a portion of the first insulating layer is positioned between the first layer and the first insulating portion.

4. The isolator according to claim 2 , wherein
the first layer is insulative, and
the first layer is provided also between the first metal portion and the first insulating layer.

5. The isolator according to claim 1 , wherein
the first layer includes carbon, silicon, and at least one selected from the group consisting of oxygen and nitrogen,
the first insulating layer includes nitrogen and silicon, and
a carbon concentration in the first layer is higher than a carbon concentration in the first insulating layer.

6. The isolator according to claim 2 , wherein the first insulating layer is not provided between the first layer and the first insulating portion.

7. The isolator according to claim 1 , wherein the first layer is not provided between the first metal portion and the first insulating portion.

8. The isolator according to claim 7 , wherein the first layer is conductive or semiconductive.

9. The isolator according to claim 1 , further comprising a second layer provided around a bottom portion of the third portion,
the third portion being provided on the second portion with a second conductive layer interposed,
the second layer contacting the second conductive layer,
the second layer including silicon and carbon.

10. The isolator according to claim 1 , further comprising:
a second layer provided around a bottom portion of the third portion; and
a second insulating layer provided on the second layer,
the third portion being provided on the second portion with a second conductive layer interposed,
the second layer contacting the second conductive layer,
a Young's modulus of the second layer being lower than a Young's modulus of the second insulating layer.

11. The isolator according to claim 1 , wherein the first metal portion and the second metal portion are provided in spiral configurations along a plane perpendicular to the first direction.

12. The isolator according to claim 11 , wherein one end of the first metal portion is electrically connected to the first portion, or one end of the second metal portion is electrically connected to the third portion.

13. The isolator according to claim 1 , wherein the first metal portion and the second metal portion are provided in flat plate configurations along a plane perpendicular to the first direction.

14. The isolator according to claim 1 , further comprising:
a first circuit electrically connected to the first metal portion; and
a second circuit electrically connected to the second metal portion.

15. A digital isolator, comprising:
a first metal portion;
a first insulating portion provided on the first metal portion;
a second metal portion provided on the first insulating portion;
a third metal portion including
a first portion provided around the first metal portion in a direction perpendicular to a first direction, the first direction being from the first metal portion toward the second metal portion,
a second portion provided on a portion of the first portion with a first conductive layer interposed, and
a third portion provided on the second portion and provided around the second metal portion in the perpendicular direction;

a first layer contacting the first conductive layer and an other portion of the first portion and being provided around a bottom portion of the second portion; and
a first insulating layer provided between the first metal portion and the first insulating portion,
a Young's modulus of the first layer being lower than a Young's modulus of the first insulating layer.

16. The isolator according to claim 15 , wherein the first layer includes silicon and carbon.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Ohguro Tatsuya
• Oda Tatsuhiro
• Ootsuka Kenichi

Classifications

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/423

  Shielding layers · CPC title

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D62/113 Primary

  Isolations within a component, i.e. internal isolations · CPC title