Array substrate and fabrication method thereof, and display device

Patent metadata

Field	Value
Publication number	US-11404332-B2
Application number	US-201816090396-A
Country	US
Kind code	B2
Filing date	Jan 23, 2018
Priority date	Jun 28, 2017
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

The present disclosure provides an array substrate, a fabrication method thereof and a display device. The array substrate includes an insulating layer provided with a first via therein. The array substrate further includes a detection structure including a first conductive structure, a second conductive structure and an insulating structure therebetween. The insulating structure is a portion of the insulating layer. The second conductive structure includes a first portion and a second portion which are separated from each other, and the first portion and the second portion partially overlap with the first conductive structure in a thickness direction of the array substrate, respectively. A second via is provided in the insulating structure between overlapping portions of the first portion and the first conductive structure, and a third via is provided in the insulating structure between overlapping portions of the second portion and the first conductive structure.

First claim

The invention claimed is:

1. An array substrate having a display area and a non-display area,
wherein the array substrate comprises a gate insulating layer provided with a first via therein, and a gate metal layer and a data layer and a data line on opposite sides of the gate insulating layer,
the insulating layer extends from the non-display area to the display area of the array substrate, the first via is within the non-display area,
the array substrate further comprises a detection structure in the non-display area, the detection structure comprising a first conductive structure, a second conductive structure and an insulating structure between the first conductive structure and the second conductive structure, the insulating structure being a portion of the gate insulating layer, the first conductive structure being a portion of the gate metal layer, and the second conductive structure being a portion of the data line,
the second conductive structure comprises a first portion and a second portion which are separated from each other, the first portion and the second portion partially overlapping with the first conductive structure in a thickness direction of the array substrate, respectively,
a second via is provided in the insulating structure between overlapping portions of the first portion and the first conductive structure, and a third via is provided in the insulating structure between overlapping portions of the second portion and the first conductive structure, and
the first portion is configured to receive a test signal, and the second portion is configured to provide an output signal.

2. The array substrate of claim 1 , wherein the array substrate comprises a plurality of detection structures which are uniformly distributed.

3. A display device comprising an array substrate, wherein the array substrate has a display area and a non-display area, and comprises a gate insulating layer provided with a first via therein, and a gate metal layer and a data line on opposite sides of the gate insulating layer,
the insulating layer extends from the non-display area to the display area of the array substrate, the first via is within the non-display area,
the array substrate further comprises a detection structure in the non-display area, the detection structure comprising a first conductive structure, a second conductive structure and an insulating structure between the first conductive structure and the second conductive structure, the insulating structure being a portion of the gate insulating layer, the first conductive structure being a portion of the gate metal layer, and the second conductive structure being a portion of the data line,
the second conductive structure comprises a first portion and a second portion which are separated from each other, the first portion and the second portion partially overlapping with the first conductive structure in a thickness direction of the array substrate, respectively,
a second via is provided in the insulating structure between overlapping portions of the first portion and the first conductive structure, and a third via is provided in the insulating structure between overlapping portions of the second portion and the first conductive structure, and
the first portion is configured to receive a test signal, and the second portion is configured to provide an output signal.

4. A fabrication method of an array substrate, the array substrate being the array substrate of claim 1 , the fabrication method comprising steps of:
forming a pattern of the first conductive structure of the detection structure while forming a pattern of the first conductive layer;
forming a pattern of the insulating structure of the detection structure while forming a pattern of the gate insulating layer;
forming the second via and the third via in the pattern of the insulating structure of the detection structure while forming the first via in the pattern of the gate insulating layer;
forming a pattern of the second conductive structure of the detection structure while forming a pattern of the second conductive layer, the second conductive structure comprising a first portion and a second portion which are separated from each other, wherein
the first portion and the second portion partially overlap with the first conductive structure in a thickness direction of the array substrate, respectively,
the second via is formed in the insulating structure between overlapping portions of the first portion and the first conductive structure, and the third via is formed in the insulating structure between overlapping portions of the second portion and the first conductive structure, and
the first portion is configured to receive a test signal, and the second portion is configured to provide an output signal.

5. The fabrication method of claim 4 , wherein the first conductive structure is a portion of the first conductive layer, the insulating structure is a portion of the insulating layer, and the second conductive structure is a portion of the second conductive layer.

6. The fabrication method of claim 4 , wherein
the first conductive layer, a gate electrode and a gate line are formed simultaneously using a same material;
and
the second conductive layer is a data line metal layer.

7. The fabrication method of claim 5 , wherein
the first conductive layer, a gate electrode and a gate line are formed simultaneously using a same material;
and
the second conductive layer is a data line metal layer.

8. A detection method of an array substrate, the array substrate being the array substrate of claim 1 , the detection method comprising steps of:
inputting a test signal to the first portion of the second conductive structure;
detecting the test signal output from the second portion of the second conductive structure;
determining whether there is residual material of the insulating layer in the first via of the insulating layer according to whether the test signal is output from the second portion of the second conductive structure.

9. The detection method of claim 8 , wherein the array substrate comprises a plurality of detection structures which are uniformly distributed.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Cao Binbin

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title