Interconnect structures and methods of fabrication

Patent metadata

Field	Value
Publication number	US-11404307-B2
Application number	US-201916586279-A
Country	US
Kind code	B2
Filing date	Sep 27, 2019
Priority date	Sep 27, 2019
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.

First claim

What is claimed is:

1. An integrated circuit interconnect structure, comprising:
a first interconnect in a first metallization level;
a first dielectric adjacent to at least a portion of the first interconnect, wherein the first dielectric comprises nitrogen and has a first carbon content;
a second interconnect in a second metallization level above the first metallization level, the second interconnect comprising a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect and in contact with a portion of the first dielectric;
a second dielectric adjacent to at least a portion of the second interconnect and directly adjacent to the first dielectric and in contact with a portion of the uppermost surface of the first interconnect, wherein the second dielectric comprises nitrogen and has a second carbon content; and
wherein the first carbon content increases with distance away from the lowermost surface of the second interconnect and wherein the second carbon content increases with distance away from the uppermost surface of the first interconnect.

2. The integrated circuit interconnect structure of claim 1 , wherein the first dielectric further comprises silicon and oxygen, and the second dielectric further comprises silicon and oxygen.

3. The integrated circuit interconnect structure of claim 1 , wherein the first carbon content increases to between 2 at. % and 30 at. % of the first dielectric and wherein the second carbon content increases to between 2 at. % and 30 at. % of the second dielectric.

4. The integrated circuit interconnect structure of claim 2 , wherein the first dielectric and the second dielectric have substantially the same chemical composition.

5. The integrated circuit interconnect structure of claim 1 , wherein the first dielectric has a vertical thickness of between 2 nm and 20 nm and the second dielectric has a vertical thickness of between 2 nm and 20 nm.

6. The integrated circuit interconnect structure of claim 1 , wherein the first carbon content increases over a distance of 1 nm or less to a maximum carbon content within a remainder of the first dielectric.

7. The integrated circuit interconnect structure of claim 1 , wherein the first interconnect comprises a wide upper portion and a narrow lower portion, wherein the second interconnect comprises a narrow upper portion and wide lower portion and wherein the wide upper portion of the first interconnect is in contact with the wide lower portion of the second interconnect.

8. The integrated circuit interconnect structure of claim 1 , further comprising:
a third dielectric adjacent to the first interconnect and below the first dielectric, wherein the third dielectric comprises a material with less carbon content than the first dielectric; and
a fourth dielectric adjacent to the second interconnect and above the second dielectric wherein the fourth dielectric comprises a material with less carbon content than the second dielectric.

9. The integrated circuit interconnect structure of claim 1 ,
further comprising a third dielectric adjacent to the first interconnect and below the first dielectric, wherein the third dielectric comprises a material with less carbon content than the first dielectric; and
wherein the interface between the first dielectric and the third dielectric is nonplanar.

10. The integrated circuit interconnect structure of claim 1 , further comprising:
a third dielectric adjacent to the first dielectric and adjacent to the sidewall of the first interconnect, wherein the third dielectric comprises a material with less carbon content and less nitrogen content than the first dielectric material.

11. The integrated circuit interconnect structure of claim 1 , wherein the first metallization level further comprises a third interconnect adjacent to the first dielectric and spatially distant from the first interconnect and wherein the third interconnect has an uppermost surface that is substantially coplanar with the uppermost surface of the first interconnect.

12. The integrated circuit interconnect structure of claim 11 , wherein the second metallization level further comprises a fourth interconnect adjacent to the second dielectric and spatially distant from the second interconnect, wherein the fourth interconnect has a lowermost surface that is substantially coplanar with the lowermost surface of the second interconnect, and wherein the uppermost surface of the third interconnect is in contact with a portion of the lowermost surface of the fourth interconnect.

13. The integrated circuit interconnect structure of claim 12 , wherein the third interconnect is spatially distant from the first interconnect by an amount that is substantially equal to an amount the fourth interconnect is spatially distant from the second interconnect.

14. The integrated circuit interconnect structure of claim 11 , wherein the second interconnect is an interconnect line segment and wherein uppermost surfaces of the first interconnect and the third interconnect are directly adjacent to, and in contact with, first portions of a lowermost surface of the interconnect line segment, and wherein the first dielectric is directly adjacent to, and in contact with, a second portion of the lowermost surface of the interconnect line segment, the second portion between the first portions.

15. A system comprising:
a processor;
a radio transceiver coupled to the processor, wherein at least one of the processor or the transceiver comprises:
a transistor comprising:
a drain contact coupled to a drain;
a source contact coupled to a source; and
a gate contact coupled to a gate; and
the integrated circuit interconnect structure of claim 1 coupled with the drain contact.

16. The system of claim 15 , further comprising a battery coupled to power at least one of the processor or radio transceiver.

17. A method of fabricating an integrated circuit interconnect structure, the method comprising:
preparing a first substrate, the preparing comprising:
forming a first material layer stack comprising a first dielectric and a second dielectric comprising nitrogen and carbon on the first dielectric;
forming an opening in the first material layer stack;
depositing a first conductive material in the opening;
planarizing the first conductive material and an upper surface of the second dielectric; and
reducing a content of the carbon in the second dielectric over a distance from the upper surface of the second dielectric;

preparing a second substrate, the preparing comprising:
forming a second material layer stack comprising a third dielectric and a fourth dielectric comprising nitrogen and carbon on the third dielectric;
forming an opening in the second material layer stack;
depositing a second conductive material in the opening;
planarizing the second conductive material and an upper surface of the fourth dielectric; and
reducing a content of the carbon in the fourth dielectric over a distance from the upper surface of the fourth dielectric; and

bonding the first substrate with the second substrate by bringing a surface of the first conductive material in contact with a surface of the second conductive material and with a portion of the upper surface of the fourth dielectric, the surface of the second dielectric in contact with the surface of the fourth dielectric, and the surface of the second conductive material in contact with a portion of the upper surface of the second dielectric.

18. The method of claim 17 , wherein planarizing the first conduc

Assignees

• Intel Corp

Inventors

• Chandhok Manish
• Chebiam Ramanan
• Mueller Brennen
• Carver Colin
• Bielefeld Jeffery
• Kabir Nafees
• Vreeland Richard
• Brezinski William

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title

• H10W20/093

  by modifying materials of the dielectric parts · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title