Semiconductor device packaging warpage control

Patent metadata

Field	Value
Publication number	US-11404288-B1
Application number	US-202117209710-A
Country	US
Kind code	B1
Filing date	Mar 23, 2021
Priority date	Mar 23, 2021
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a panel by placing a plurality of semiconductor die on a major side of a carrier substrate and encapsulating with an encapsulant the plurality semiconductor die and the major side of the carrier substrate. A plurality of warpage control features are formed with the encapsulant while encapsulating. The method further includes placing the panel onto a warpage control fixture to substantially flatten the panel. The plurality of warpage control features interlock with mating features of the warpage control fixture.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device packaging panel, the method comprising:
forming a panel comprising:
placing a plurality of semiconductor die on a first side of a carrier substrate;
forming a plurality of warpage control features with an encapsulant, the encapsulant encapsulating the plurality of semiconductor die and the first side of the carrier substrate; and

placing the panel onto a warpage control fixture to substantially flatten the panel, the plurality of warpage control features interlocking with mating features of the warpage control fixture.

2. The method of claim 1 , further comprising forming a redistribution layer over the plurality of semiconductor die while the panel is substantially flattened on the warpage control fixture.

3. The method of claim 1 , wherein forming the panel further comprises removing the carrier substrate after forming the plurality of warpage control features.

4. The method of claim 1 , wherein tension is applied to the panel after the plurality of warpage control features are interlocked with the mating features of the warpage control fixture.

5. The method of claim 1 , wherein placing the panel onto the warpage control fixture comprises mechanically pressing the panel onto the warpage control fixture to interlock the warpage control features with the mating features.

6. The method of claim 5 , wherein the warpage control fixture includes a film, the mating features integrated into the film, and the method further comprising stretching the film to apply tension to the panel.

7. The method of claim 1 , further comprising applying heat to the panel to substantially flatten the panel before placing the panel onto the warpage control fixture.

8. The method of claim 1 , wherein the plurality of warpage control features is characterized as a plurality of cavities formed in the encapsulant and the mating features are characterized as protrusions in the warpage control fixture configured to mate with the plurality of cavities.

9. The method of claim 1 , wherein the plurality of warpage control features is characterized as a plurality of protrusions extending from a major surface of the encapsulant and the mating features are characterized as recesses configured to mate with the plurality of protrusions.

10. A method of manufacturing a semiconductor device packaging panel, the method comprising:
forming a panel comprising:
placing a plurality of semiconductor die on a first side of a carrier substrate;
encapsulating with an encapsulant the plurality semiconductor die and the first side of the carrier substrate;
forming a plurality of warpage control features with the encapsulant during the encapsulating; and

placing the panel onto a warpage control fixture, the plurality of warpage control features interlocking with mating features of the warpage control fixture to substantially flatten the panel.

11. The method of claim 10 , further comprising:
removing the carrier substrate after forming the plurality of warpage control features; and
forming a redistribution layer over the plurality of semiconductor die while the panel is substantially flattened on the warpage control fixture.

12. The method of claim 10 , further comprising applying tension to the panel by way of a film incorporated in the warpage control fixture to substantially flatten the panel, the mating features integrated into the film.

13. The method of claim 10 , wherein the plurality of warpage control features is characterized as a plurality of protrusions extending from a major surface of the encapsulant.

14. The method of claim 10 , further comprising applying heat to the panel to substantially flatten the panel before placing the panel onto the warpage control fixture.

15. The method of claim 10 , further comprising removing the warpage control features by way of singulating semiconductor device units from the panel, each semiconductor device unit comprising at least one semiconductor die.

16. A method of manufacturing a semiconductor device packaging panel, the method comprising:
forming a panel comprising:
placing a plurality of semiconductor die on a first side of a carrier substrate;
encapsulating with an encapsulant the plurality semiconductor die and the first side of the carrier substrate;
forming a plurality of warpage control features with the encapsulant during the encapsulating;

placing the panel onto a warpage control fixture, the warpage control fixture including mating features configured to interlock with the plurality of warpage control features; and
applying tension to the panel to substantially flatten the panel.

17. The method of claim 16 , wherein tension is applied to the panel by way of stretching a film incorporated in the warpage control fixture, the mating features integrated into the film.

18. The method of claim 16 , further comprising applying heat to the panel to substantially flatten the panel before placing the panel onto the warpage control fixture, the warpage control fixture comprising a rigid structure with the mating features incorporated thereon, the tension applied to the panel by way of the panel cooling while the warpage control features are interlocked with the mating features.

19. The method of claim 16 , further comprising:
removing the carrier substrate after forming the plurality of warpage control features; and
forming a redistribution layer over the plurality of semiconductor die while the panel is substantially flattened on the warpage control fixture.

20. The method of claim 16 , wherein at least a portion of the plurality of warpage control features is characterized as a plurality of protrusions extending from a major surface of the encapsulant or characterized as a plurality of cavities formed in the encapsulant.

Assignees

• Nxp Usa Inc

Inventors

• Vincent Michael B
• Hayes Scott M
• Gong Zhiwei
• Gupta Vivek
• Gan Richard Te

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title