Method for manufacturing coreless substrate

Patent metadata

Field	Value
Publication number	US-11399440-B2
Application number	US-202017038898-A
Country	US
Kind code	B2
Filing date	Sep 30, 2020
Priority date	Jun 24, 2020
Publication date	Jul 26, 2022
Grant date	Jul 26, 2022

Abstract

A temporary carrier according to an embodiment of the present invention may include a core layer, a first Cu foil layer and a second Cu foil layer on surfaces of both sides of the core layer. Each of the first Cu foil layer and the second Cu foil layer may include double Cu foils which are physically attached together.

First claim

What is claimed is:

1. A method for manufacturing a coreless substrate, the method comprising:
(a) manufacturing the temporary carrier, comprising:
(a1) laminating a first Cu foil layer and a second Cu foil layer onto both surfaces of a core layer, wherein each of the first Cu foil layer and the second Cu foil layer comprises double Cu foils which includes an inner layer Cu foil and an outer layer Cu foil which are physically laminated and attached together; and
(a2) coating a photoresist layer onto the first Cu foil layer and the second Cu foil layer and performing exposure and development to the photoresist layer, wherein each edge of the photoresist layer is spaced from the corresponding edge of the first and second Cu foil layers by a distance to form an exposed outer edge region;
(b) performing layer building up operations on both sides of the temporary carrier;
(c) overall cutting along a cutting line coincident with an outer peripheral edge of the inner layer Cu foil; and
(d) separating the double Cu foils from each other to remove the temporary carrier, and thus obtaining a first coreless substrate and a second coreless substrate.

2. The method according to claim 1 , wherein the step (a) further comprises:
(a5) after removing the photoresist layer, applying an etching resisting layer onto the surface of the first and second Cu foil layers, wherein the etching resisting layer covers the outer edge region.

3. The method according to claim 2 , further comprising:
(e) etching off the inner layer Cu coil and the etching resisting layer on the first coreless substrate and the second coreless substrate.

4. The method according to claim 1 , wherein the core layer comprises at least one layer of prepreg or a Cu clad laminate interposed between the prepregs.

5. The method according to claim 1 , wherein the step (d) comprises separating the outer layer Cu foil and the inner layer Cu coil by applying an external mechanical force therebetween.

6. The method according to claim 5 , wherein, when separating the outer layer Cu foil and the inner layer Cu coil by the external mechanical force, a separating angle between the outer layer Cu foil and the inner layer Cu coil is 30 to 60 degrees.

Assignees

• Zhuhai Access Semiconductor Co Ltd

Inventors

• Chen Xianming
• Peng Jian
• Zhang Jida
• Huang Benxia
• Feng Lei
• Xie Bingsen
• Gao Jun

Classifications

• H05K2201/0355

  Metal foils · CPC title

• H05K1/036

  Multilayers with layers of different types · CPC title

• H05K3/4602

  characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated · CPC title

• H05K3/4682 Primary

  Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil · CPC title

• H05K3/022

  Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates · CPC title