Solid-state imaging device and imaging apparatus including same

Patent metadata

Field	Value
Publication number	US-11399148-B2
Application number	US-202016817159-A
Country	US
Kind code	B2
Filing date	Mar 12, 2020
Priority date	Sep 14, 2017
Publication date	Jul 26, 2022
Grant date	Jul 26, 2022

Abstract

A solid-state imaging device includes: a plurality of pixels arranged in a matrix on a semiconductor substrate, wherein each of the plurality of pixels includes: a photoelectric converter that converts received light into a signal charge; a plurality of read gates that each read the signal charge from the photoelectric converter; a plurality of charge accumulators that each accumulate the signal charge read by any one of the plurality of read gates; and a charge holder that receives, from one of the plurality of charge accumulators, transfer of the signal charge accumulated in the charge accumulator, holds the signal charge, and transfers, to one of the plurality of charge accumulators, the signal charge held.

First claim

What is claimed is:

1. A solid-state imaging device, comprising:
a pixel on a semiconductor substrate, wherein:
the pixel includes:
a photoelectric converter that converts received light into a signal charge;
a plurality of read gates that each read the signal charge from the photoelectric converter;
a plurality of charge accumulators that each accumulate the signal charge read by any one of the plurality of read gates; and
a charge holder that is arranged apart from a transfer channel in a direction orthogonal to a direction in which the transfer channel extends, and that receives and holds the signal charge from one of the plurality of charge accumulators, and transfers the signal charge to one of the plurality of charge accumulators,

the plurality of read gates include a first read gate and a second read gate, and
the solid-state imaging device comprises a timing generator that performs interchange of a location in which a first signal charge is accumulated and a location in which a second signal charge is accumulated in a case where the first read gate reads the first signal charge and the second read gate reads the second signal charge, and
the timing generator performs the interchange a plurality of times, to cause a total number of times the first signal charge is transferred to the charge holder and a total number of times the second signal charge is transferred to the charge holder to be equal.

2. The solid-state imaging device according to claim 1 , comprising:
a plurality of pixels arranged in a matrix, the plurality of pixels each being the pixel,
wherein in the plurality of pixels, the signal charge is read from the photoelectric converter in a same direction in a row direction in arrangement of the plurality of pixels.

3. The solid-state imaging device according to claim 1 ,
wherein each of the plurality of charge accumulators includes a part of a transfer channel for transferring the signal charge and a part of a transfer electrode overlapping with the part of the transfer channel in a planar view of the semiconductor substrate, and
the transfer channel per one pixel comprises one transfer channel.

4. The solid-state imaging device according to claim 1 ,
wherein the first read gate and the second read gate respectively read the first signal charge and the second signal charge, with a first phase difference.

5. The solid-state imaging device according to claim 4 ,
wherein the plurality of charge accumulators include a first charge accumulator and a second charge accumulator, and
the timing generator performs the interchange, after the first read gate reads the first signal charge to the first charge accumulator and the second read gate reads the second signal charge to the second charge accumulator with the first phase difference.

6. The solid-state imaging device according to claim 5 ,
wherein the first read gate reads the signal charge to the second charge accumulator and the second read gate reads the signal charge to the first charge accumulator, with a second phase difference that differs by 180 degrees in phase from the first phase difference.

7. The solid-state imaging device according to claim 1 ,
wherein the timing generator performs the interchange in a signal read period.

8. The solid-state imaging device according to claim 1 ,
wherein the charge holder includes at least a part of a charge holding channel, and at least a part of a charge holding gate overlapping with the at least a part of the charge holding channel in a planar view of the semiconductor substrate, and
a negative voltage is applied to the charge holding gate to cause pinning of an interface between the charge holding channel and the charge holding gate in at least a part of a period except a period in which the charge holder holds the signal charge.

9. The solid-state imaging device according to claim 1 ,
wherein at least a part of the charge holder is covered with a light shielding film.

10. The solid-state imaging device according to claim 1 ,
wherein the pixel further includes:
a charge holder reset drain that discharges at least a part of the signal charge from the charge holder; and
a charge holder reset gate that controls the discharge to the charge holder reset drain.

11. The solid-state imaging device according to claim 1 ,
wherein the pixel further includes:
an overflow drain that discharges at least a part of the signal charge from the photoelectric converter; and
an exposure control gate that controls the discharge to the overflow drain.

12. An imaging apparatus, comprising:
the solid-state imaging device according to claim 1 ;
a light source that emits infrared light in a pulse form at a plurality of timings; and
a processor that generates a distance image based on an output signal of the solid-state imaging device.

Assignees

• Panasonic Ip Man Co Ltd
• Nuvoton Technology Corp Japan

Inventors

• Suzuki Sei
• Matsuo Junichi

Classifications

• G01S7/4865 Primary

  Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak (peak detection in noise, signal conditioning G01S7/487) · CPC title

• H04N25/771 Primary

  comprising storage means other than floating diffusion · CPC title

• H04N25/622

  by controlling anti-blooming drains · CPC title

• H04N25/53

  Control of the integration time · CPC title

• H04N25/75

  Circuitry for providing, modifying or processing image signals from the pixel array · CPC title