Semiconductor devices and related methods

Patent metadata

Field	Value
Publication number	US-11398455-B2
Application number	US-201916429553-A
Country	US
Kind code	B2
Filing date	Jun 3, 2019
Priority date	Jun 3, 2019
Publication date	Jul 26, 2022
Grant date	Jul 26, 2022

Abstract

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The second internal interconnect can be coupled to the second electronic device and the first electronic device. The encapsulant can cover the substrate inner sidewall and the device stack, and can fill the cavity. Other examples and related methods are disclosed herein.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate comprising:
a first substrate side,
a second substrate side opposite the first substrate side,
a substrate outer sidewall between the first substrate side and the second substrate side, and
a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side;

a device stack in the cavity and comprising:
a first electronic device; and
a second electronic device stacked on the first electronic device;

a first internal interconnect coupled to the substrate and the device stack;
a second internal interconnect coupled to the second electronic device and the first electronic device;
an encapsulant that covers the substrate inner sidewall and the device stack, and fills the cavity;
an external interconnect coupled to the substrate and being entirely external to the substrate having the cavity in which the device stack is located;
a vertical interconnect coupled to the first substrate side and bounded by the encapsulant;
wherein the encapsulant comprises an encapsulant top side having an opening that exposes the vertical interconnect; and
wherein the encapsulant is flush with a sidewall of the vertical interconnect, and a top end of the vertical interconnect is substantially coplanar with the encapsulant top side;
a base substrate;
a module stack comprising:
a first module on the base substrate, the first module comprising the substrate, the device stack, the first and second internal interconnects, and the encapsulant; and
a second module on the first module, the second module comprising a second substrate with a second cavity, a second device stack in the second cavity, and a second encapsulant covering the second device stack and filling the second cavity; a base encapsulant covering the base substrate and the module stack; and an underfill in the base encapsulant between the first module and the second module, and between a top side of the base substrate and a bottom side of the first module and contacting a sidewall of the first module and a sidewall of the second module.

2. The semiconductor device of claim 1 , wherein:
a bottom of the device stack is exposed from the encapsulant.

3. The semiconductor device of claim 1 , wherein:
the second substrate side is coplanar with a bottom of the encapsulant and with a bottom of the device stack.

4. The semiconductor device of claim 1 , wherein:
the encapsulant covers the first substrate side.

5. The semiconductor device of claim 1 , wherein:
a top side of the first electronic device is lower than the first substrate side; and
a top side of the second electronic device is lower than the first substrate side.

6. The semiconductor device of claim 5 , wherein:
the device stack comprises a third electronic device stacked on the second electronic device; and
a top side of the third electronic device is higher than the first substrate side.

7. The semiconductor device of claim 1 , wherein:
the device stack comprises a third electronic device stacked on the second electronic device;
a top side of the first electronic device comprises first device terminals;
a top side of the second electronic device comprises second device terminals;
a top side of the third electronic device comprises third device terminals;
the first substrate side comprises a first substrate terminal;
the device stack comprises an offset configuration where:
the second electronic device covers a majority of a top side of the first electronic device but exposes the first device terminals; and
the third electronic device covers a majority of a top side of the second electronic device but exposes the second device terminals;

the first internal interconnect is coupled to a first one of the first device terminals and to the first substrate terminal;
the second internal interconnect is coupled to a first one of the second device terminals and to a second one of the first device terminals; and
a third internal interconnect coupled to a first one of the third device terminals and to a second one of the second device terminals.

8. The semiconductor device of claim 1 , wherein:
the encapsulant covers the substrate outer sidewall.

9. The semiconductor device of claim 1 , wherein:
the first internal interconnect comprises a first end coupled to the substrate and a second end coupled to the device stack; and
a height of the first end is higher than a height of the second end.

10. The semiconductor device of claim 1 , wherein:
the device stack comprises a third electronic device stacked on the second electronic device;
a thickness of the first electronic device is greater than a thickness of the second electronic device; and
a thickness of the second electronic device is same as a thickness of the third electronic device.

11. The semiconductor device of claim 1 , wherein:
the second electronic device is stacked on a first side of the first electronic device;
the device stack comprises a third electronic device stacked on a second side of the first electronic device; and
the third electronic device comprises:
a sidewall exposed from the encapsulant; and
a side that faces away from the first electronic device and is exposed from the encapsulant.

12. The semiconductor device of claim 1 , wherein:
the substrate comprises:
a substrate vertical portion comprising the first substrate side; and
a substrate ledge portion comprising the second substrate side; and

the substrate ledge portion comprises a ledge that defines a first width of the cavity;
the substrate vertical portion defines a second width of the cavity greater than the first width; and
the first internal interconnect is coupled to the substrate ledge portion.

13. The semiconductor device of claim 1 , wherein:
the first substrate side is exposed from the encapsulant.

14. The semiconductor device of claim 1 , comprising:
a base substrate;
a module stack comprising:
a first module on the base substrate and comprising the substrate, the device stack, the first and second internal interconnects, and the encapsulant; and
a second module on the first module and comprising a second substrate with a second cavity, a second device stack in the second cavity, and a second encapsulant covering the second device stack and filling the second cavity; and

a base encapsulant covering the base substrate and the module stack;
wherein the encapsulant of the second module is between a bottom of the second device stack and a top of the device stack of the first module.

15. A method comprising:
receiving a substrate comprising:
a first substrate side,
a second substrate side opposite the first substrate side,
a substrate outer sidewall between the first substrate side and the second substrate side, and
a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side;

providing a device stack in the cavity and comprising:
a first electronic device; and
a second electronic device stacked on the first electronic device;

providing a first internal interconnect coupled to the substrate and the device stack;
providing a second internal interconnect coupled to the second electronic device and the first electronic device;
providing an encapsulant that covers the substrate inner sidewall and the device stack, and fills the cavity;
providing an external interconnect coupled to the substrate and being entirely external to the substrate having the cavity in which the device stack is located; and
providing a vertical in

Assignees

• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Han Gyu Wan
• Bang Won Bae
• Lee Ju Hyung
• Chang Min Hwa
• Park Dong Joo
• Khim Jin Young
• Kim Jae Yun
• Hong Se Hwan
• Yu Seung Jae
• Bowers Shaun
• Lim Gi Tae
• Cho Byoung Woo
• Choi Myung Jea
• Lee Seul Bee

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title