HBM silicon photonic TSV architecture for lookup computing AI accelerator

Patent metadata

Field	Value
Publication number	US-11398453-B2
Application number	US-201815911063-A
Country	US
Kind code	B2
Filing date	Mar 2, 2018
Priority date	Jan 9, 2018
Publication date	Jul 26, 2022
Grant date	Jul 26, 2022

Abstract

According to one general aspect, an apparatus may include a memory circuit die configured to store a lookup table that converts first data to second data. The apparatus may also include a logic circuit die comprising combinatorial logic circuits configured to receive the second data. The apparatus may further include an optical via coupled between the memory circuit die and the logical circuit die and configured to transfer second data between the memory circuit die and the logic circuit die.

First claim

What is claimed is:

1. An apparatus comprising:
a memory circuit die configured to store a lookup table that converts first data to second data;
a logic circuit die comprising logic circuits configured to receive the second data; and
an optical via coupled between the memory circuit die and the logical circuit die and configured to transfer second data between the memory circuit die and the logic circuit die, and
wherein the apparatus is configured to produce the first data with the logic circuits, transfer the first data across the optical via to the memory circuit die, and convert the first data to the second data based on the lookup table.

2. The apparatus of claim 1 , wherein the memory circuit die comprises:
a driver circuit configured to receive an electrical version of second data;
an optical modulator configured to vary a light source according to, at least in part, an electrical version of second data; and
wherein the optical modulator is coupled with a waveguide portion of the optical via.

3. The apparatus of claim 1 , wherein the memory circuit die comprises:
an optical detector configured to detect optical data transmitted across a waveguide portion of the optical via, and convert the optical data to electrical data; and
an amplifier circuit to provide electrical gain to the electrical data.

4. The apparatus of claim 1 , wherein the memory circuit die comprises one or more memory mats arranged in a memory bank; and
wherein the optical via is communicatively coupled with the memory bank to select the memory bank for data transmitted across the optical via.

5. The apparatus of claim 1 , wherein the memory circuit die comprises a memory mat; and
wherein the optical via is communicatively coupled with the memory mat, wherein the memory mat is associated with a form of modulation such that a data transfer using the form of modulation is directed to the memory mat.

6. The apparatus of claim 1 , wherein the logic circuit die comprises:
a scheduler circuit configured to coordinate inter-die data traffic across the optical via.

7. The apparatus of claim 1 , wherein the optical via comprises a through-silicon-photonic-via; and
wherein the memory circuit die comprises a reconfigurable lookup table.

8. The apparatus of claim 1 , wherein the logic circuit die comprises:
one or more first logic circuits configured to generate the first data,
an optical transmitter configured to convert the first data from electrical form to optical form, and transmit the optical first data to the memory circuit die,
an optical receiver configured to receive the second data and convert the second data to electrical form, and
one or more second logic circuits configured to receive and process the second data; and
wherein the memory circuit die comprises:
the lookup table comprising a dynamically reconfigurable logic operation configured to convert the first data to the second data, and
a transducer configured to convert data between electrical and optical forms.

9. An apparatus comprising:
a first circuit die configured to store a reconfigurable logic circuit;
a second circuit die comprising one or more logic circuits configured to transform input data to first data, wherein the input data is received at the second circuit die; and
an optical link coupled between the first circuit die and the second circuit die, and configured to transfer the first data between the first die and the second die;
wherein the reconfigurable logic circuit is configured to process the first data with a first efficiency;
wherein the second circuit die is configured to process the first data with a second efficiency; and
wherein the second circuit die is configured to perform a determination that the first efficiency is greater than the second efficiency, and transfer, based on the determination that the first efficiency is greater than the second efficiency, the first data across the optical link to the first circuit die, to process the first data by the reconfigurable logic circuit.

10. The apparatus of claim 9 , wherein the second circuit die comprises:
a driver circuit configured to receive an electrical version of the first data from the one or more logic circuits;
an optical modulator configured to vary a light source according to, at least in part, the electrical version of the first data; and
wherein the optical modulator is coupled with the optical link.

11. The apparatus of claim 9 , wherein the first circuit die comprises:
an optical detector configured to detect optical data transmitted across the optical link, and convert the optical data to electrical data; and
an amplifier circuit to provide electrical gain to the electrical data, and provide the electrical data to the reconfigurable logic circuit.

12. The apparatus of claim 9 , wherein the reconfigurable logic circuit comprises at least one memory mat arranged in a memory bank; and
wherein the optical link is communicatively coupled with the memory bank.

13. The apparatus of claim 9 , wherein the reconfigurable logic circuit comprises a memory mat; and
wherein the optical link is communicatively coupled with the memory mat, wherein the memory mat is associated with a form of modulation such that a data transfer using the form of modulation is directed to the memory mat.

14. The apparatus of claim 9 , wherein the second circuit die comprises:
a scheduler circuit configured to coordinate inter-die data traffic across the optical link.

15. The apparatus of claim 9 , wherein the optical link comprises a through-silicon-photonic-via; and
wherein the reconfigurable logic circuit comprises a lookup table.

16. A multi-chip module comprising:
a light source configured to generate an optical signal;
a logic circuit die comprising a fixed logic circuit, and configured to transmit data, in an optical fashion to a memory circuit die;
an interposer layer configured to couple the light source with the logic circuit die;
a memory circuit die configured to store a lookup table that receives the data; and
an optical via coupled between the memory circuit die and the logic circuit die and configured to transfer data between the memory circuit die and the logic circuit die.

17. The multi-chip module of claim 16 , further comprising:
an electrical via coupled between the memory circuit die and the logic circuit die and configured to transfer address information between the memory circuit die and the logic circuit die.

18. The multi-chip module of claim 16 , further comprising:
a second memory circuit die configured to store a second lookup table; and
a second optical via coupled between the memory circuit die and the second memory circuit die and configured to transfer data between the memory circuit die and the second memory circuit die.

19. The multi-chip module of claim 16 , wherein the fixed logic circuit comprises:
a logic circuit configured to process data, and
a dispatcher circuit configured to transfer data from the optical via to the logic circuit.

20. The multi-chip module of claim 16 , further comprising a scheduler circuit configured to coordinate the transfer of data across the optical via.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Gu Peng
• Malladi Krishna
• Zheng Hongzhong

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/295

  optical coupling · CPC title

• H10W90/00 Primary

  Package configurations · CPC title