Radar device, monitoring device, phase control circuit and method for monitoring a signal processing circuit

Patent metadata

Field	Value
Publication number	US-11397240-B2
Application number	US-201916554066-A
Country	US
Kind code	B2
Filing date	Aug 28, 2019
Priority date	Sep 5, 2018
Publication date	Jul 26, 2022
Grant date	Jul 26, 2022

Abstract

One example of a radar device includes a phase-locked loop for generating a radiofrequency signal. The phase-locked loop has a multi-modulus divider. The radar device furthermore comprises a delta-sigma modulator for generating a modulated signal for the multi-modulus divider, and a signal generator for generating an input signal for the delta-sigma modulator. The radar device has monitoring circuits, wherein a first monitoring circuit is configured to monitor a locked state of the phase-locked loop, a second monitoring circuit is configured to monitor the delta-sigma modulator, and a third monitoring circuit is configured to monitor the signal generator.

First claim

What is claimed is:

1. A radar device, comprising:
a phase-locked loop configured to generate a radio frequency signal, wherein the phase-locked loop includes a multi-modulus divider;
a delta-sigma modulator configured to generate a modulated signal for the multi-modulus divider;
a signal generator configured to generate an input signal for the delta-sigma modulator;
a first monitoring circuit configured to monitor a locked state of the phase-locked loop;
a second monitoring circuit configured to monitor the delta-sigma modulator; and
a third monitoring circuit configured to monitor the signal generator.

2. The radar device as claimed in claim 1 , wherein the first monitoring circuit implements a first monitoring method, the second monitoring circuit implements a second monitoring method different from the first monitoring method, and the third monitoring circuit implements a third monitoring method different from the first monitoring method and the second monitoring method.

3. The radar device as claimed in claim 1 , wherein the first monitoring circuit is configured to output first information that indicates an out-of-lock state of the phase-locked loop, wherein the second monitoring circuit is configured to output second information that indicates an incorrect behavior of the delta-sigma modulator, and wherein the third monitoring circuit is configured to output third information that indicates an incorrect behavior of the signal generator.

4. The radar device as claimed in claim 1 , wherein the third monitoring circuit is configured to use hash values to monitor the signal generator.

5. The radar device as claimed in claim 1 , wherein the second monitoring circuit is configured to use a comparison between an input signal and an output signal of the delta-sigma modulator to monitor the delta-sigma modulator.

6. The radar device as claimed in claim 1 , wherein the first monitoring device comprises:
a first counter that is configured to count output signals of the multi-modulus divider to generate a first count value; and
a second counter that is configured to count output signals of a reference clock to generate a second count value, wherein the first monitoring device is configured to compare the first count value with the second count value.

7. The radar device as claimed in claim 1 , wherein the first, the second, and the third monitoring devices are configured to output a respective error information signal in a case of detecting an incorrect functionality of the phase-locked loop, the delta-sigma modulator, and the signal generator, respectively.

8. A monitoring device configured to monitor a functionality of a signal processing circuit, the monitoring device comprising:
a first signal input configured to receive an output signal of a signal generator;
a second signal input configured to receive a modulated signal generated by a delta-sigma modulator in the signal processing circuit, wherein the delta-sigma modulated signal is based on the output signal of the signal generator; and
a comparison circuit that is configured to receive the output signal of the signal generator and the modulated signal and compare the modulated signal with the output signal in order to monitor a correct signal generation of the delta-sigma modulator based on a comparison result,
wherein the output signal of the signal generator is a sequence of digital signals that represent successively incremented rational numbers, and
wherein the modulated signal comprises a sequence of natural numbers generated based on the sequence of digital signals.

9. The monitoring device as claimed in claim 8 , wherein the monitoring device is configured to generate a comparison value for monitoring the delta-sigma modulator based on data received by the first signal input and based on data received by the second signal input.

10. The monitoring device as claimed in claim 9 , further comprising:
a signal output, wherein the monitoring device is configured to output an error information signal via the signal output if the comparison value lies outside of a predetermined tolerance range.

11. The monitoring device as claimed in claim 8 , wherein the output signal of the signal generator is a sequence of digital signals for controlling a frequency ramp.

12. The monitoring device as claimed in claim 11 ,
wherein the sequence of digital signals comprises rational numbers, including whole numbers and fractions, and
wherein the modulated signal comprises a sequence of natural numbers.

13. The monitoring device as claimed in claim 8 , wherein the modulated signal is an input signal for a multi-modulus divider of a phase-locked loop of a radar sensor.

14. The monitoring device as claimed in claim 8 , wherein an average value or an accumulated value of the sequence of natural numbers is equal to an average value or an accumulated value of the successively incremented rational numbers, respectively, in the absence of a fault.

15. The monitoring device as claimed in claim 8 , wherein the modulated signal is configured to control a division ratio of a frequency divider.

16. A monitoring device configured to monitor a functionality of a signal processing circuit, the monitoring device comprising:
a first signal input configured to receive an output signal of a signal generator;
a second signal input configured to receive a modulated signal generated using a delta-sigma modulator in the signal processing circuit, wherein the modulated signal is based on the output signal of the signal generator; and
a comparison circuit that is configured to monitor a correct signal generation of the signal processing circuit based on the output signal of the signal generator and the modulated signal,
wherein the monitoring device is configured to generate a comparison value for monitoring the signal processing circuit based on data received by the first signal input and based on data received by the second signal input,
wherein the output signal of the signal generator is a sequence of digital signals for controlling a frequency ramp, and
wherein the monitoring device is configured to generate the comparison value based on values of the sequence of digital signals in order to control the frequency ramp within a time interval between a first digital signal and a second digital signal, wherein the first digital signal controls a beginning of the frequency ramp and the second digital signal controls an end of the frequency ramp.

17. A phase control circuit, comprising:
a signal generator configured to generate an output signal;
a signal processing circuit comprising a delta-sigma modulator configured to generate a modulated signal based on the output signal; and
a monitoring device configured to monitor a functionality of the signal processing circuit, the monitoring device comprising:
a first signal input configured to receive the output signal of the signal generator;
a second signal input configured to receive the modulated signal generated by the delta-sigma modulator; and
a comparison circuit that is configured to receive the output signal of the signal generator and the modulated signal and monitor a correct signal generation of the signal processing circuit based on a comparison of the output signal of the signal generator and the modulated signal,
wherein a signal output of the signal generator from which the output signal is output is connected to the first signal input of the monitoring device and to an input of the signal processing circuit, and
wherein a signal output of the signal processing circuit from

Assignees

• Infineon Technologies Ag

Inventors

• Greslehner-Nimmervoll Bernhard
• Gstoettenbauer Bernhard
• Heschl Lukas
• Koutsouradis Evangelos
• Onic Alexander

Classifications

• G01S13/28

  with time compression of received pulses · CPC title

• G01S7/032

  Constructional details for solid-state radar subsystems · CPC title

• G01S7/35 Primary

  Details of non-pulse systems · CPC title

• G01S7/4004 Primary

  of parts of a radar system · CPC title

• H03L7/197

  a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)} · CPC title