Generation of fast frequency ramps

Patent metadata

Field	Value
Publication number	US-10320402-B2
Application number	US-201715843589-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	Dec 16, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.

First claim

What is claimed is:

1. A phase locked loop (PLL) circuit comprising:
a voltage-controlled oscillator configured to generate a radio frequency (RF) oscillator signal based on a control voltage;
a feedback loop configured to provide a feedback signal based on the RF oscillator signal, the feedback loop comprising a fractional-N frequency divider, a phase detector and a loop filter, wherein a division ratio of the fractional-N frequency divider is set based on a digital input signal, which is a sequence of digital words; and
a digital-to-analog conversion unit configured to receive the digital input signal and to generate an analog output signal, the digital-to-analog conversion unit comprising a pre-processing stage configured to pre-process the sequence of digital words, a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal, and circuitry configured to combine the analog output signal and the feedback signal to generate the control voltage,
wherein the pre-processing stage includes a word-length adaption unit configured to generate the pre-processed sequence of digital words by reducing the word-lengths of the digital words in the sequence of digital words and further includes a sigma-delta modulator coupled to the word-length adaption unit downstream thereof, the sigma-delta modulator being configured to modulate the pre-processed sequence of digital words having reduced word-lengths and output the pre-processed sequence of digital words, as modulated, to the digital-to-analog-converter.

2. The PLL circuit of claim 1 , wherein the digital-to-analog conversion unit further comprises a post-processing stage coupled to the digital-to-analog-converter downstream thereof.

3. The PLL circuit of claim 2 , wherein the post-processing stage comprises at least a low-pass filter.

4. The PLL circuit of claim 1 , wherein the digital-to-analog conversion unit is a current-steering digital-to-analog converter.

5. The PLL circuit of claim 1 , wherein the pre-processing stage further comprises a decimator configured to reduce a clock rate of the sequence of digital words by a decimation factor.

6. The PLL circuit of claim 1 , wherein the pre-processing stage further comprises a pre-distortion unit configured to pre-distort digital information included in the sequence of digital words to compensate for a non-linear characteristic of the voltage-controlled oscillator.

7. The PLL circuit of claim 1 , wherein the digital-to-analog conversion unit has a control input receiving an adjustable gain value, and wherein the adjustable gain value is set by the word-length adaption unit.

8. The PLL circuit of claim 1 , wherein the word-length adaption unit is configured to reduce the word-length of the digital words of the sequence of digital words by extracting, from the digital word and at a selectable bit position of the digital word, a digital word with reduced word-length.

9. The PLL circuit of claim 8 , wherein the word-length adaption unit is further configured to set a gain of the digital-to-analog conversion unit depending on the bit position.

10. The PLL circuit of claim 1 , wherein the circuitry configured to combine the analog output signal and the feedback signal is part of the loop filter.

11. The PLL circuit of claim 10 , wherein the output of the digital-to-analog conversion unit is coupled to an integrator stage of the loop filter.

12. The PLL circuit of claim 11 , wherein the integrator stage of the loop filter is coupled between an input of the loop filter and a reference circuit node, to which the analog output signal of the digital-to-analog conversion unit is supplied.

13. A method comprising:
generating an RF oscillator signal using an RF oscillator that is coupled in a phase-locked loop, the phase-locked loop configured to generate a feedback signal for the RF oscillator based on a digital input signal, which is a sequence of digital words;
converting the digital input signal to an analog output signal, wherein the converting comprises reducing word-lengths of the digital words in the sequence of digital words, sigma-delta modulating the sequence of digital words having reduced word-lengths, and converting the modulated sequence of digital words of reduced word-lengths to obtain the analog output signal; and
combining the analog output signal and the feedback signal to generate a control signal for the RF oscillator.

14. The method of claim 13 , further comprising:
reducing a clock rate of the sequence of digital words by a decimation factor.

15. The method of claim 13 , further comprising:
pre-distorting digital information included in the sequence of digital words to compensate for a non-linear characteristic of the RF oscillator.

16. The method of claim 13 , further comprising:
filtering the analog output signal.

17. A circuit comprising:
an RF oscillator coupled in a phase-locked loop, the phase-locked loop configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal; and
a digital-to-analog conversion unit configured to receive the digital input signal and to generate an analog output signal, the digital-to-analog conversion unit comprising a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal, and circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator,
wherein the pre-processing stage includes a word-length adaption unit configured to generate the pre-processed sequence of digital words by reducing the word-lengths of the digital words in the sequence of digital words and further includes a sigma-delta modulator coupled to the word-length adaption unit downstream thereof, the sigma-delta modulator being configured to modulate the pre-processed sequence of sequence of digital words having reduced word-lengths and output the pre-processed sequence of digital words, as modulated, to the digital-to-analog-converter.

18. The circuit of claim 17 , wherein the phase-locked loop comprises a feedback loop configured to receive an RF oscillator signal and to provide the feedback signal, the feedback loop comprising a fractional-N frequency divider configured to effect a division ratio, which is based on the digital input signal.

19. The circuit of claim 18 , wherein the feedback loop further comprises a phase detector and a loop filter that provides the feedback signal at its output.

20. The circuit of claim 18 , wherein the pre-processing stage further comprises a decimator configured to reduce a clock rate of the sequence of digital words by a decimation factor.

Assignees

• Infineon Technologies Ag

Inventors

• Stuhlberger Rainer
• Heschl Lukas

Classifications

• H03L7/146 Primary

  by using digital means for generating the oscillator control signal (H03L7/141, H03L7/143 take precedence) · CPC title

• H03G3/3047

  for intermittent signals, e.g. burst signals · CPC title

• G01S2013/9321

  Velocity regulation, e.g. cruise control · CPC title

• H03L7/0814

  the phase shifting device being digitally controlled · CPC title

• G01S13/343

  using sawtooth modulation · CPC title