Method for manufacturing electronic chips

Patent metadata

Field	Value
Publication number	US-11393786-B2
Application number	US-202017111198-A
Country	US
Kind code	B2
Filing date	Dec 3, 2020
Priority date	Dec 4, 2019
Publication date	Jul 19, 2022
Grant date	Jul 19, 2022

Abstract

A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.

First claim

The invention claimed is:

1. A method for manufacturing electronic chips, comprising:
depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin;
forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit;
forming metal connection pillars by filling the cavities with metal, each of the metal connection pillars directly and physically contacting a respective contact pad at an upper surface of a respective integrated circuit; and
separating the integrated circuits into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.

2. The method of claim 1 , wherein the depositing the protective resin and forming the at least one cavity includes:
forming, on the side of the upper face of the semiconductor substrate, at least one pillar of sacrificial resin per integrated circuit, in contact with the upper face of the integrated circuit;
depositing, on the side of the upper face of the substrate, the protective resin extending between the pillars of sacrificial resin; and
forming the cavities in the protective resin by selectively removing the pillars of sacrificial resin with respect to the protective resin.

3. The method according to claim 1 , wherein the depositing the protective resin and forming the at least one cavity includes:
depositing the protective resin on the side of the upper face of the substrate; and
forming the cavities in the protective resin by laser drilling.

4. The method according to claim 1 , wherein the filling the cavities with metal is realized by a non-electrolytic deposition method.

5. The method according to claim 1 , wherein the metal used for filling the cavities is a tin-based alloy.

6. The method according to claim 2 , wherein the forming the at least one pillar of sacrificial resin includes:
depositing a film of sacrificial resin on the side of the upper face of the substrate; and
etching the film and retaining only the pillars of sacrificial resin.

7. The method according to claim 6 , wherein the film of sacrificial resin is a photosensitive resin.

8. The method according to claim 7 , wherein, the etching the film of sacrificial resin includes etching the film of sacrificial resin by photolithography to form pillars of sacrificial resin.

9. The method according to claim 1 , further comprising:
forming, on the side of the upper face of the semiconductor substrate, trenches laterally separating the integrated circuits, prior to the depositing the protective resin and forming the at least one cavity.

10. The method according to claim 9 , wherein the deposited protective resin extends in the trenches.

11. The method according to claim 10 , further comprising:
prior to the separating the integrated circuits into individual chips, thinning the substrate from a lower face of the substrate until the protective resin at the bottom of the trenches is reached,
wherein the cut lines extend across from the trenches.

12. The method according to claim 11 , further comprising, after the thinning the substrate and before the separating the integrated circuits into individual chips, depositing a rear-face protective resin on the lower face of the substrate.

13. A method, comprising:
forming a protective resin on a surface of a semiconductor substrate, the semiconductor substrate including a plurality of integrated circuits at the surface;
exposing portions of each of the plurality of integrated circuits at the surface by selectively removing portions of the protective resin;
forming a plurality of metal connection pillars, each of the metal connection pillars directly and physically contacting a respective integrated circuit at the surface, adjacent ones of the metal connection pillars spaced laterally apart from one another by the protective resin; and
separating the integrated circuits into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.

14. The method according to claim 13 , wherein the selectively removing portions of the protective resin includes forming cavities in the protective resin by laser drilling.

15. The method according to claim 14 , wherein the forming the plurality of metal connection pillars includes filling the cavities with metal.

16. The method according to claim 15 , wherein the filling the cavities with metal is realized by a non-electrolytic deposition method.

17. The method according to claim 15 , wherein the metal is a tin-based alloy.

18. A method, comprising:
laterally separating a plurality of integrated circuits from one another by forming a plurality of trenches in a substrate;
forming a protective resin on a surface of the substrate;
forming a plurality of cavities in the protective resin, each of the cavities exposing a portion of a respective one of the integrated circuits at the surface of the substrate;
forming metal connection pillars by filling the cavities with metal, each of the metal connection pillars directly and physically contacting a respective one of the integrated circuits at the surface of the substrate; and
separating the integrated circuits into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.

19. The method according to claim 18 , further comprising:
forming a plurality of pillars of sacrificial resin on the surface of the substrate,
wherein forming the protective resin includes depositing, on the surface of the substrate, the protective resin extending between the pillars of sacrificial resin, and
wherein forming the cavities includes selectively removing the pillars of sacrificial resin with respect to the protective resin.

20. The method according to claim 18 , wherein the forming the plurality of cavities in the protective resin includes forming the plurality of cavities by laser drilling.

Assignees

• St Microelectronics Tours Sas

Inventors

• Fallourd Ludovic
• Serre Christophe

Classifications

• H10W72/0198 Primary

  batch processes · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/936

  Multiple bond pads having different shapes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title