Ppower semiconductor device with anticorrosive edge termination structure

Patent metadata

Field	Value
Publication number	US-11387359-B2
Application number	US-201916713392-A
Country	US
Kind code	B2
Filing date	Dec 13, 2019
Priority date	Dec 14, 2018
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 μm. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.

First claim

What is claimed is:

1. A power semiconductor device having a power semiconductor transistor configuration and comprising:
a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge;
an active region configured to conduct a load current between the first load terminal structure and the second load terminal structure in a conducting state of the power semiconductor device;
an edge termination region separating the active region from the lateral chip edge;
a hard passivation layer arranged at the front side in at least a portion of the edge termination region; and
a soft passivation layer arranged above a portion of the hard passivation layer,
wherein at the front-side, the edge termination region comprises a protection region which does not comprise any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 μm,
wherein in a blocking state of the power semiconductor device, the protection region is configured to accommodate a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.

2. The power semiconductor device of claim 1 , wherein in a vertical cross-section, the protection region extends along the lateral direction from a starting point to the lateral chip edge, and wherein the starting point is located at a distance of at most 30 μm from an outermost point where a doped semiconductor region is in contact with a metal and/or polysilicon layer that is electrically connected with the first load terminal structure.

3. The power semiconductor device of claim 1 , wherein the hard passivation layer comprises an oxide layer having an oxide layer thickness, and wherein the hard passivation layer extends further towards the active region than the protection region at most by a lateral distance of 10 times the oxide layer thickness.

4. The power semiconductor device of claim 1 , wherein the hard passivation layer does not laterally extend further towards the active region than the protection region.

5. A power semiconductor device, comprising:
a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge;
an active region configured to conduct a load current between the first load terminal structure and the second load terminal structure in a conducting state of the power semiconductor device;
an edge termination region separating the active region from the lateral chip edge;
an insulation layer arranged at the front side, wherein a lateral edge of the insulation layer defines a contact hole, the contact hole being filled with a metal and/or polysilicon layer that is in contact with a doped semiconductor region of the semiconductor body; and
a hard passivation layer that is formed from a hard passivation material and arranged at the front side at least in a portion of the edge termination region such that the hard passivation layer does not extend above the lateral edge of the insulation layer and the hard passivation layer at least partially covers the polysilicon and/or metal layer,
wherein the contact hole is defined by a second lateral edge of the insulation layer that is opposite the lateral edge of the insulation layer, and
wherein the power semiconductor device is configured such that no regions of the hard passivation material which at least partially cover the polysilicon and/or metal layer extend over the lateral edge or the second lateral edge.

6. The power semiconductor device of claim 5 , wherein the hard passivation layer is arranged exclusively between the contact hole and the lateral chip edge.

7. The power semiconductor device of claim 5 , wherein the hard passivation layer comprises an oxide layer having an oxide layer thickness, and wherein the hard passivation layer laterally terminates at a minimum distance of at least once the oxide layer thickness from a vertical projection of the lateral edge of the insulation layer.

8. The power semiconductor device of claim 5 , further comprising a metal layer electrically connected with the first load terminal structure.

9. The power semiconductor device of claim 5 , wherein the polysilicon and/or metal layer filling the contact hole is covered at least partially by a soft passivation layer.

10. A power semiconductor device, comprising:
a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge;
an active region configured to conduct a load current between the first load terminal structure and the second load terminal structure in a conducting state of the power semiconductor device;
an edge termination region separating the active region from the lateral chip edge;
a hard passivation layer arranged at the front side at least in a portion of the edge termination region, the hard passivation layer comprising an oxide layer having an oxide layer thickness;
a metal layer arranged at the front side at least in a portion of the edge termination region and having a lateral edge; and
an insulation layer arranged at the front side at least in a portion of the edge termination region,
wherein a lateral edge of the insulation layer is covered by the metal layer,
wherein in a cross-section along a vertical direction pointing from the front side to the backside, the cross-section is perpendicular to the lateral edge and a common lateral extension range of the hard passivation layer and the metal layer amounts to at most 10 times the oxide layer thickness,
wherein the common lateral extension range does not extend across any lateral edge of the insulation layer within the edge termination region.

11. The power semiconductor device of claim 10 , wherein at any lateral edge of the metal layer in the edge termination region, in a vertical cross-section perpendicular to the lateral edge, the common lateral extension range of the hard passivation layer and the metal layer amounts to at most 10 times the oxide layer thickness.

12. The power semiconductor device of claim 10 , wherein the common lateral extension range amounts to at most 10 times a metal layer thickness of the metal layer at the lateral edge.

13. The power semiconductor device of claim 10 , wherein the metal layer forms at least a portion of a gate runner electrode.

14. The power semiconductor device of claim 10 , wherein the metal layer establishes an electrical connection between a drainage cell and the first load terminal structure.

15. The power semiconductor device of claim 10 , wherein the hard passivation layer comprises a nitride layer.

16. The power semiconductor device of claim 10 , further comprising a soft passivation layer arranged above at least a portion of the hard passivation layer.

17. The power semiconductor device of claim 10 , further comprising an edge termination structure arranged at the front side and configured to laterally terminate an electric field that is present in the semiconductor body in a blocking state of the power semiconductor device, and wherein the hard passivation layer is arranged above at least a portion of the edge termination structure.

18. The power semiconductor device of claim 17 , wherein the edge termination struc

Assignees

• Infineon Technologies Ag

Inventors

• Humbel Oliver
• Bauer Josef-Georg
• Brandenburg Jens
• Car Diana
• Koch Philipp Sebastian
• Koprowski Angelika
• Kremp Sebastian
• Kurzmann Thomas
• Lercher Erwin
• Ruething Holger

Classifications

• H10D64/232

  Emitter electrodes for IGBTs · CPC title

• H10D62/127 Primary

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D12/441

  Vertical IGBTs · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title