Tri-gate architecture multi-nanowire confined transistor

Patent metadata

Field	Value
Publication number	US-11387329-B2
Application number	US-201816147275-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

Transistor structures including a fin structure having multiple graded III-N material layers with polarization layers therebetween, integrated circuits including such transistor structures, and methods for forming the transistor structures are discussed. The transistor structures further include a source, a drain, and a gate coupled to the fin structure. The fin structure provides a multi-gate multi-nanowire confined transistor architecture.

First claim

What is claimed is:

1. A transistor structure comprising:
a fin structure comprising first and second graded group III-nitride (III-N) material layers with a polarization layer therebetween, the first graded III-N material layer comprising first and second group III constituents, wherein the first graded III-N material layer comprises a graded first group III constituent concentration profile with a decreasing concentration of the first group III constituent along a height of the fin structure;
a source and a drain coupled to the fin structure; and
a gate between the source and the drain and coupled to the fin structure.

2. The transistor structure of claim 1 , wherein the first graded III-N material layer comprises indium gallium nitride, the first group III constituent comprises indium, and the graded first group III constituent concentration profile comprises an indium concentration of not less than 15% in a first region of the first graded III-N material layer distal from the polarization layer and not more than 1% in a second region of the first graded III-N material layer proximal to the polarization layer.

3. The transistor structure of claim 2 , wherein the indium concentration in the second region is 0% and the second region comprises gallium nitride.

4. The transistor structure of claim 1 , wherein the first graded III-N material layer comprises indium gallium nitride, the first group III constituent comprises indium, and the graded first group III constituent concentration profile comprises an indium concentration of not less than 99% in a first region of the first graded III-N material layer distal from the polarization layer and not more than 50% in a second region of the first graded III-N material layer proximal to the polarization layer.

5. The transistor structure of claim 1 , wherein the polarization layer is on the first graded III-N material layer, the second graded III-N material layer is on the polarization layer, and the fin structure further comprises a second polarization layer on the second graded III-N material layer, a third graded III-N material layer on the second polarization layer, and a third polarization layer on the third graded III-N material layer.

6. The transistor structure of claim 5 , wherein the first, second, and third graded III-N material layers each comprise indium gallium nitride having graded concentration profiles comprising indium concentrations of not less than 15% at base regions of the first, second, and third graded III-N material layers and not more than 1% at top regions of the first, second, and third graded III-N material layers.

7. The transistor structure of claim 1 , wherein the graded first group III constituent concentration profile comprises a first concentration per depth rate of change of the first group III constituent proximal to a top surface of the first graded III-N material layer and a second concentration per depth rate of change of the first group III constituent proximal to a bottom surface of the first graded III-N material layer, wherein both the first and second per depth rate of changes are along a depth of the fin structure opposite the height of the fin structure, and wherein the first concentration per depth rate of change is greater than the second concentration per depth rate of change.

8. The transistor structure of claim 1 , wherein the polarization layer comprises aluminum indium gallium nitride having an aluminum concentration of not less than 70% and an indium concentration of not more than 17%.

9. The transistor structure of claim 1 , wherein the fin structure has a width of not more than 6 nm, the first and second graded III-N material layers have heights of not less than 5 nm and not more than 30 nm, and the polarization layer has a height of not less than 1 nm and not more than 4 nm.

10. The transistor structure of claim 1 , further comprising:
a second fin structure substantially parallel to the fin structure, the second fin structure comprising third and fourth graded III-N material layers and a second polarization layer therebetween, wherein the source, the drain, and the gate are coupled to the second fin structure, and wherein the third graded III-N material layer comprises the graded first group III constituent concentration profile.

11. The transistor structure of claim 10 , further comprising:
first and second sidewall structures on at least a first base portion of the fin structure and third and fourth sidewall structures on at least a second base portion of the second fin structures; and
a field insulator between the first sidewall structure and the third sidewall structure and under the source.

12. A system comprising:
a memory; and
an integrated circuit coupled to the memory, the integrated circuit comprising a transistor structure comprising:
a fin structure comprising first and second graded group III-nitride (III-N) material layers with a polarization layer therebetween, the first graded III-N material layer comprising first and second group III constituents, wherein the first graded III-N material layer comprises a graded first group III constituent concentration profile with a decreasing concentration of the first group III constituent along a height of the fin structure;
a source and a drain coupled to the fin structure; and
a gate between the source and the drain and coupled to the fin structure.

13. The system of claim 12 , wherein the first graded III-N material layer comprises indium gallium nitride, the first group III constituent comprises indium, and the graded concentration profile comprises an indium concentration of not less than 15% in a first region of the first graded III-N material layer distal from the polarization layer and not more than 1% in a second region of the first graded III-N material layer proximal to the polarization layer.

14. The system of claim 12 , wherein the first graded III-N material layer comprises indium gallium nitride, the first group III constituent comprises indium, and the graded concentration profile comprises an indium concentration of not less than 99% in a first region of the first graded III-N material layer distal from the polarization layer and not more than 50% in a second region of the first graded III-N material layer proximal to the polarization layer.

15. The system of claim 12 , wherein the integrated circuit comprises a wireless transceiver operable in the GHz band.

16. The system of claim 12 , further comprising a battery coupled to the integrated circuit.

17. A method of forming a transistor structure comprising:
growing, over a substrate, a first graded III-N material layer, a polarization layer, and a second graded III-N material layer, wherein the polarization layer is between the first and second graded III-N material layers, the first graded III-N material layer comprises first and second group III constituents, and the first graded III-N material layer comprises a graded first group III constituent concentration profile with a decreasing concentration of the first group III constituent along a height extending from the substrate;
patterning the first graded III-N material layer, the polarization layer, and the second graded III-N material layer to form a fin structure;
forming a gate coupled to the fin structure; and
forming a source and a drain coupled to the fin structure, wherein the gate is between the source and the drain.

18. The method of forming the transistor structure of claim 17 , wherein the first graded III-N material layer comprises indium gallium nitride, the first

Assignees

• Intel Corp

Inventors

• Then Han Wui
• Radosavljevic Marko
• Dasgupta Sansaptak
• Fischer Paul
• Hafez Walid

Classifications

• H10D30/47

  having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title