Nonvolatile memory device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11387249-B2
Application number	US-201916708482-A
Country	US
Kind code	B2
Filing date	Dec 10, 2019
Priority date	Dec 3, 2008
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a substrate including a first region and a second region;
an electrode structure including a plurality of electrodes vertically stacked on the substrate, the electrode structure having a stair step structure on the second region,
a plurality of first vertical layers penetrating the electrode structure on the first region;
at least one second vertical layer penetrating and supporting the electrode structure on the second region; and
a plurality of bit lines crossing the electrode structure in the first region and connected to the plurality of first vertical layers,
wherein the at least one second vertical layer is free of connection with any bit line, and
wherein the electrodes of the first region and the electrodes of the second region comprise different conductive materials.

2. The nonvolatile memory device of claim 1 , wherein the electrodes of the first region comprise polysilicon, and the electrodes of the second region comprise metal material that is lower in specific resistance than polysilicon.

3. The nonvolatile memory device of claim 2 , wherein the electrodes of the second region comprise tungsten (W), aluminum (Al), titanium (Ti), or tantalum (Ta).

4. The nonvolatile memory device of claim 2 , wherein uppermost of the electrodes of both the first region and the second region comprise metal material.

5. The nonvolatile memory device of claim 2 , further comprising a plurality of contact plugs on the second region and connected to respective ones of the plurality of electrodes, and a plurality of conductive lines connected to the plurality of contact plugs.

6. The nonvolatile memory device of claim 5 , wherein respective top surfaces of the plurality of conductive lines are coplanar with respective top surfaces of the plurality of bit lines.

7. The nonvolatile memory device of claim 5 , wherein the at least one second vertical layer is between a first group comprising the plurality of first vertical layers and a second group comprising the plurality of contact plugs, in a cross-sectional view.

8. The nonvolatile memory device of claim 5 , wherein the at least one second vertical layer is closer to the plurality of first vertical layers than to the plurality of contact plugs.

9. The nonvolatile memory device of claim 1 , wherein the at least one second vertical layer comprises a dielectric supporter and is spaced apart from the stair step structure.

10. The nonvolatile memory device of claim 1 , wherein the at least one second vertical layer and the plurality of first vertical layers each comprise an equal length in a vertical direction.

11. The nonvolatile memory device of claim 10 , wherein the at least one second vertical layer is not in the stair step structure of the electrode structure.

12. The nonvolatile memory device of claim 1 , wherein the at least one second vertical layer comprises a plurality of second vertical layers having different respective vertical lengths in the second region.

13. The nonvolatile memory device of claim 12 , wherein the vertical lengths decrease with increasing distance from the first region.

14. A nonvolatile memory device comprising:
a substrate including a first region and a second region;
an electrode structure including a plurality of electrodes vertically stacked on the substrate, the electrode structure having a stair step structure on the second region,
a plurality of first vertical layers penetrating the electrode structure on the first region;
a plurality of contact plugs on the stair step structure and connected to respective ones of the plurality of electrodes;
at least one second vertical layer penetrating the electrode structure between the first region and the second region;
a plurality of bit lines crossing the electrode structure in the first region and connected to the plurality of first vertical layers; and
a plurality of conductive lines connected to the plurality of contact plugs,
wherein the at least one second vertical layer is free of connection with any bit line, and
wherein the at least one second vertical layer is spaced apart from the stair step structure.

15. The nonvolatile memory device of claim 14 , wherein respective top surfaces of the plurality of conductive lines are coplanar with respective top surfaces of the plurality of bit lines.

16. The nonvolatile memory device of claim 14 , wherein the at least one second vertical layer is between a first group comprising the plurality of first vertical layers and a second group comprising the plurality of contact plugs, in a cross-sectional view.

17. The nonvolatile memory device of claim 14 , wherein the at least one second vertical layer and the plurality of first vertical layers each comprise an equal length in a vertical direction.

18. The nonvolatile memory device of claim 14 , wherein the electrodes of the first region and the electrodes of the second region comprise different conductive materials.

19. A nonvolatile memory device comprising:
a substrate including a first region and a second region;
an electrode structure including a plurality of electrodes vertically stacked on the substrate, the electrode structure having a stair step structure on the second region,
a plurality of first vertical layers penetrating the electrode structure on the first region;
at least one second vertical layer penetrating and supporting the electrode structure on the second region; and
a plurality of bit lines crossing the electrode structure in the first region and connected to the plurality of first vertical layers,
wherein the at least one second vertical layer comprises a dielectric supporter and is free of connection with any bit line.

20. The nonvolatile memory device of claim 19 , wherein the at least one second vertical layer is between the stair step structure and the plurality of first vertical layers.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chae Soodoo
• Lee Myoungbum
• Moon Huichang
• Kim Hansoo
• Kim Jingyun
• Kim Kihyun
• Choi Siyoung
• Cho Hoosung

Classifications

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D64/118

  Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title