Semiconductor storage device and control method of semiconductor storage device

Patent metadata

Field	Value
Publication number	US-11386971-B2
Application number	US-202017012118-A
Country	US
Kind code	B2
Filing date	Sep 4, 2020
Priority date	Mar 23, 2020
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A semiconductor storage device according to the present embodiment includes an antifuse element and a first element. The antifuse element is connected at one end to a first terminal to which a write voltage is applicable, and includes a gate oxide film. The first element is connected to the other end of the antifuse element. In a case where the write voltage that breaks the gate oxide film is supplied to the first terminal and the gate oxide film is not broken, the first element supplies a second potential that makes a potential difference between the one end and the other end less than a potential that breaks the gate oxide film, to the other end.

First claim

The invention claimed is:

1. A semiconductor storage device comprising:
an antifuse element connected at one end to a first terminal to which a write voltage is applicable, and including a gate oxide film;
a first element connected to the other end of the antifuse element, wherein the first element is a first transistor connected at one end to the other end of the antifuse element
a second transistor connected at one end to the other end of the first transistor; and
a third transistor connected at one end to the other end of the second transistor and having the other end to which a reference potential is supplied,
wherein film thicknesses of gate oxide films of the antifuse element, the first transistor, the second transistor, and the third transistor are about equal, and
in a case where the write voltage that breaks the gate oxide film of the antifuse element is applied to the first terminal and the gate oxide film of the antifuse element is not broken, a potential that makes a potential difference between the first terminal and the other end of the antifuse element less than a potential that breaks the gate oxide film of the antifuse element is applied to a gate of the first transistor.

2. The device of claim 1 , wherein back gates of the first and second transistors are open, and
in a case where the gate oxide film is not broken, a voltage between the other end of the antifuse element and the one end of the third transistor is divided by the first transistor and the second transistor.

3. The device of claim 1 , wherein the first transistor and the second transistor are MOS transistors.

4. The device of claim 1 , wherein in a case where the gate oxide film is not broken, a gate voltage that makes the other end of the antifuse element have the second potential is applied to a gate of the first transistor.

5. The device of claim 4 , further comprising a first voltage generation circuit capable of supplying the write voltage to the first terminal.

6. The device of claim 5 , wherein the first voltage generation circuit includes a plurality of level shifter circuits.

7. The device of claim 5 , further comprising a second voltage generation circuit configured to generate the gate voltage.

8. The device of claim 7 , further comprising a power supply circuit capable of supplying a voltage to the first voltage generation circuit and the second voltage generation circuit.

9. A semiconductor storage device comprising:
an antifuse element connected at one end to a first terminal to which a write voltage is applicable, and including a gate oxide film;
a first element connected to the other end of the antifuse element, wherein the first element is a level shifter circuit;
a fourth transistor connected at one end to the other end of the antifuse element and
a fifth transistor connected at one end to the other end of the fourth transistor and having the other end to which a reference potential is supplied,
wherein film thicknesses of gate oxide films of the antifuse element, the fourth, and the fifth transistor are about equal, and
in a case where the write voltage that breaks the gate oxide film of the antifuse element is applied to the first terminal and the gate oxide film of the antifuse element is not broken, the level shifter circuit supplies the second potential that makes a potential difference between the first terminal and the other end of the antifuse element less than a potential that breaks the gate oxide film of the antifuse element.

10. A control method of a semiconductor storage device including an antifuse element that is connected at one end to a first terminal to which a write voltage is applicable and that has a gate oxide film,
a first element connected to the other end of the antifuse element, wherein the first element is a first transistor connected at one end to the other end of the antifuse element;
a second transistor connected at one end to the other end of the first transistor; and
a third transistor connected at one end to the other end of the second transistor and having the other end to which a reference potential is supplied,
wherein film thicknesses of gate oxide films of the antifuse element, the first transistor, the second transistor, and the third transistor are about equal, the method comprising,
in a case where the write voltage that breaks the gate oxide film is applied to the first terminal and the gate oxide film is not broken,
dividing a voltage between the other end of the antifuse element and the other end of the third transistor by the first transistor, the second transistor, and the third transistor, and
controlling the first element to supply a second potential that makes a potential difference between the one end and the other end of the antifuse element less than a potential that breaks the gate oxide film of the antifuse element, to the other end.

11. The method of claim 10 , wherein back gates of the first and second transistors are open, and
in a case where the gate oxide film is not broken, a voltage between the other end of the antifuse element and the one end of the third transistor is divided by the first transistor and the second transistor.

12. The method of claim 11 , wherein the first transistor and the second transistor are MOS transistors.

13. The method of claim 11 , wherein in a case where the gate oxide film is not broken, a gate voltage that makes the other end of the antifuse element have the second potential is applied to a gate of the first transistor.

14. The method of claim 13 , wherein a first voltage generation circuit of the semiconductor storage device is capable of supplying the write voltage to the first terminal.

15. The method of claim 14 , wherein the first voltage generation circuit includes a plurality of level shifter circuits.

16. The method of claim 15 , wherein a second voltage generation circuit of the semiconductor storage device generates the gate voltage.

17. The method of claim 16 , wherein a power supply circuit of the semiconductor storage device is capable of supplying a voltage to the first voltage generation circuit and the second voltage generation circuit.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Tamura Motoki

Classifications

• G11C17/16

  using electrically-fusible links · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title