Temperature variation compensation

Patent metadata

Field	Value
Publication number	US-11385802-B2
Application number	US-202016833310-A
Country	US
Kind code	B2
Filing date	Mar 27, 2020
Priority date	Mar 4, 2016
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

First claim

What is claimed is:

1. A device comprising:
a memory; and
a controller coupled to the memory, the controller configured to:
write data to a first portion of a block of a memory stack of the memory; and
in response to detecting an average temperature change that exceeds a block variation threshold after writing the data to the block, wherein the average temperature change is determined by averaging a first temperature change of a first memory die of the memory stack and a second temperature change of a second memory die of the memory stack:
close the block to additional write operations to an unused portion of the block, and
continue to allow read access to the first portion of the block.

2. The device of claim 1 , wherein the controller is further configured to write dummy data to a word line of the block prior to closing the block.

3. The device of claim 1 , wherein the controller is further configured to store a default value of a read voltage and to determine an adjusted read voltage to read data from the memory, the adjusted read voltage determined based on the default value and based on a data structure that maps read voltage offset values to differences between write temperatures and read temperatures.

4. The device of claim 3 , wherein the data structure includes a table and wherein each entry of the table is accessible according to a write temperature range and a read temperature range.

5. The device of claim 4 , wherein the table omits read voltage offset values for entries that correspond to matching write temperature ranges and read temperature ranges.

6. The device of claim 1 , wherein the controller is further configured to read multiple codewords of data from the memory and, in response to detecting an error rate exceeding a threshold error rate for a threshold number of the codewords, to initiate a temperature compensation operation that modifies one or more memory access parameters based on a temperature difference between a first temperature and a second temperature.

7. The device of claim 6 , wherein the first temperature is associated with a first time period, the first time period includes a write operation of multiple codewords to the memory, and the second temperature is associated with a second time period, the second time period includes a read operation of multiple codewords from the memory.

8. The device of claim 6 , further comprising an error correction coding (ECC) engine, and wherein the threshold error rate is less than a threshold correctable error rate of the ECC engine.

9. The device of claim 1 , wherein the memory includes:
a first memory die that includes a first temperature sensor; and
a second memory die that includes a second temperature sensor; and
wherein the controller is further configured to receive a first indicator of the first temperature from the first temperature sensor and a second indicator of the second temperature from the second temperature sensor, wherein the controller is configured to determine a temperature range based on the average temperature change.

10. The device of claim 9 , wherein the memory incudes a stack of memory dies, wherein the first memory die is a top die of the stack and wherein the second memory die is a central die of the stack.

11. A method comprising:
at a data storage device that includes a controller coupled to a non-volatile memory, performing:
writing data to a first portion of a block of a memory stack of the non-volatile memory; and
in response to detecting an average temperature change that exceeds a block variation threshold after writing the data to the block, wherein the average temperature change is determined by averaging a first temperature change of a first memory die of the memory stack and a second temperature change of a second memory die of the memory stack:
closing the block, and
continuing to allow read access to the first portion of the block.

12. The method of claim 11 , further comprising writing dummy data to a word line of the block prior to closing the block.

13. The method of claim 11 , wherein closing the block prevents write operations to an unused portion of the block.

14. The method of claim 11 , further comprising:
determining a read voltage offset value based on a data structure that maps read voltage offset values to differences between write temperatures and read temperatures; and
determining an adjusted value of a read voltage associated with reading data from the non-volatile memory, the adjusted value determined based on a default value of the read voltage and based on the read voltage offset value, wherein the data structure includes a table and wherein each entry of the table is accessible according to a write temperature range and a read temperature range.

15. The method of claim 14 , wherein the table omits read voltage offset values for entries that correspond to matching write temperature ranges and read temperature ranges.

16. The method of claim 11 , further comprising:
reading multiple codewords of data from the non-volatile memory; and
in response to detecting an error rate exceeding a threshold error rate for a threshold number of the codewords, initiating a temperature compensation operation that modifies one or more memory access parameters based on a temperature difference between a first temperature and a second temperature.

17. The method of claim 16 , wherein the first temperature is associated with a first time period, the first time period includes a write operation of multiple codewords to the memory, and the second temperature is associated with a second time period, the second time period includes a read operation of the multiple codewords from the memory.

18. The method of claim 16 , wherein the threshold error rate is less than a threshold correctable error rate of an error correction coding (ECC) engine of the data storage device.

19. The method of claim 11 , further comprising:
receiving a first indicator of the first temperature from a first temperature sensor of the first memory die of the non-volatile memory;
receiving a second indicator of the second temperature from a second temperature sensor of the second memory die of the non-volatile memory; and
determining a temperature range based on the average temperature change.

20. The method of claim 19 , wherein the non-volatile memory incudes a stack of memory dies, wherein the first die is a top die of the stack and wherein the second die is a central die of the stack.

21. A device comprising:
a memory means; and
a controller coupled to the memory means, wherein the controller is configured to:
determine an average temperature change, wherein the average temperature change is determined by averaging a first temperature change of a first memory die of the memory means and a second temperature change of a second memory die of the memory means;
detect that the average temperature change has exceeded a threshold; and
close a block of the memory means to additional write operations while continuing to allow read access to the block in response to the detecting.

Assignees

• Western Digital Tech Inc

Inventors

• Sharon Eran
• Yang Nian Niles
• Alrod Idan
• Mekhanik Evgeny
• Shlick Mark
• Lai Joanna

Classifications

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title