Topological qubit device

Patent metadata

Field	Value
Publication number	US-11380836-B2
Application number	US-202016820048-A
Country	US
Kind code	B2
Filing date	Mar 16, 2020
Priority date	Mar 16, 2020
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

Devices, systems, and/or methods that can facilitate topological quantum computing are provided. According to an embodiment, a device can comprise a circuit layer formed on a wiring layer of the device and that comprises control components. The device can further comprise a topological qubit device formed on the circuit layer and that comprises a nanorod capable of hosting Majorana fermions and a quantum well tunable Josephson junction that is coupled to the control components.

First claim

What is claimed is:

1. A device, comprising:
a circuit layer formed on a wiring layer of the device and that comprises defined components; and
a topological qubit device formed on the circuit layer, wherein the topological qubit device comprises:
a nanorod capable of hosting Majorana fermions; and
a quantum well tunable Josephson junction that is coupled to the defined components.

2. The device of claim 1 , wherein the wiring layer comprises a grid of planar wires coupled to the defined components.

3. The device of claim 1 , wherein the defined components are selected from a group consisting of control gates; Josephson junction sensing circuits; chemical potential gates; pinch gates; and Josephson junction gates.

4. The device of claim 1 , wherein the nanorod comprises a single material having superconducting properties and magnetic properties.

5. The device of claim 1 , wherein the nanorod comprises a magnetic material formed on a superconducting material.

6. The device of claim 1 , wherein the quantum well tunable Josephson junction comprises one or more semiconductor material layers.

7. A device, comprising:
a wiring layer formed on a substrate;
a circuit layer formed on the wiring layer and that comprises defined components;
a first device layer formed on the circuit layer, wherein the first device layer comprises a quantum well and electrical contacts coupled to the defined components; and
a second device layer formed on the first device layer, wherein the second device layer comprises:
nanorods capable of hosting Majorana fermions; and
electrodes, wherein the electrodes are coupled to the electrical contacts.

8. The device of claim 7 , wherein the wiring layer comprises a grid of planar wires coupled to the defined components.

9. The device of claim 7 , wherein the defined components are selected from a group consisting of one or more: control gates; Josephson junction sensing circuits; chemical potential gates; pinch gates; and Josephson junction gates.

10. The device of claim 7 , wherein the nanorods respectively comprise a single material having superconducting properties and magnetic properties.

11. The device of claim 7 , wherein the nanorods respectively comprise a magnetic material formed on a superconducting material.

12. The device of claim 7 , wherein the quantum well comprises a tunable quantum well having one or more semiconductor material layers.

13. The device of claim 7 , wherein the second device layer comprises an outermost layer of a topological qubit device, thereby facilitating at least one of reduced damage of the nanorods in fabrication, improved coherence time of the topological qubit device, improved lifespan of the topological qubit device, or improved performance of the device.

14. A method, comprising:
forming on a substrate a wiring layer;
forming on the wiring layer a circuit layer comprising defined components;
forming on the circuit layer a first device layer, the first device layer comprising a quantum well and electrical contacts coupled to the defined components; and
forming on the first device layer a second device layer, the second device layer comprising:
nanorods capable of hosting Majorana fermions; and
electrodes, wherein the electrodes are coupled to the electrical contacts.

15. The method of claim 14 , further comprising:
forming on the substrate the wiring layer comprising a grid of planar wires coupled to the defined components.

16. The method of claim 14 , further comprising:
forming on the wiring layer the circuit layer comprising the defined components that are selected from a group consisting of one or more: control gates; Josephson junction sensing circuits; chemical potential gates; pinch gates; and Josephson junction gates.

17. The method of claim 14 , further comprising:
forming on the first device layer the second device layer comprising the nanorods that respectively comprise a single material having superconducting properties and magnetic properties.

18. The method of claim 14 , further comprising:
forming on the first device layer the second device layer comprising the nanorods that respectively comprise a magnetic material formed on a superconducting material.

19. The method of claim 14 , further comprising:
forming on the circuit layer the first device layer having the quantum well comprising a tunable quantum well having one or more semiconductor material layers.

20. The method of claim 14 , further comprising:
forming on the first device layer the second device layer, the second device layer comprising an outermost layer of a topological qubit device, thereby facilitating at least one of reduced damage of the nanorods in fabrication, improved coherence time of the topological qubit device, improved lifespan of the topological qubit device, or improved performance of a device comprising the topological qubit device.

Assignees

• IBM

Inventors

• Holmes Steven J
• Philip Timothy Mathew
• Mukesh Sagarika
• Kim Youngseok
• Sadana Devendra K
• Robison Robert

Classifications

• H10D48/3835

  Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01F1/0072 Primary

  one dimensional, i.e. linear or dendritic nanostructures · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title