Memory with optimized resistive layers

Patent metadata

Field	Value
Publication number	US-11380732-B2
Application number	US-202016941885-A
Country	US
Kind code	B2
Filing date	Jul 29, 2020
Priority date	Jul 29, 2020
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

First claim

What is claimed is:

1. A memory device, comprising:
a substrate;
a plurality of memory stacks positioned on the substrate, each memory stack comprising a layered assembly of electrode materials and memory material;
a first resistive material positioned directly on the plurality of memory stacks;
a first conductive material positioned on the plurality of memory stacks over the first resistive material;
a via positioned on the substrate, the via comprising a conductive material;
a second resistive material positioned on the first conductive material and the via; and
a second conductive material positioned on the second resistive material.

2. The memory device of claim 1 , wherein a resistivity of the first resistive material is greater than a resistivity of the second resistive material.

3. The memory device of claim 1 , further comprising a dielectric material positioned in a gap of the memory device, the via extending through the dielectric material.

4. The memory device of claim 3 , further comprising a liner material positioned in the gap so as to form a barrier between the dielectric material and the first resistive material and between the dielectric material and the first conductive material.

5. The memory device of claim 1 , wherein the first resistive material and the second resistive material are a same material.

6. The memory device of claim 1 , wherein the first resistive material comprises WSiN or SiC.

7. A memory device, comprising:
a substrate;
a plurality of memory stacks positioned on the substrate, each memory stack comprising a layered assembly of electrode materials and memory material;
a via positioned on the substrate, the via comprising a conductive material;
a first resistive material positioned on the plurality of memory stacks, wherein the first resistive material covers the plurality of memory stacks and fails to cover the via;
a first conductive material positioned on the plurality of memory stacks over the first resistive material;
a second resistive material positioned on the first conductive material and the via; and
a second conductive material positioned on the second resistive material.

8. The memory device of claim 7 , wherein a resistivity of the first resistive material is greater than a resistivity of the second resistive material.

9. The memory device of claim 7 , further comprising a dielectric material positioned in a gap of the memory device, the via extending through the dielectric material.

10. The memory device of claim 7 , wherein the first resistive material and the second resistive material are a same material.

11. The memory device of claim 7 , wherein the first resistive material comprises WSiN or SiC.

12. A memory device, comprising:
a substrate;
a plurality of memory stacks positioned on the substrate, each memory stack comprising a layered assembly of electrode materials and memory material;
a via positioned on the substrate, the via comprising a conductive material;
a first resistive material positioned on the plurality of memory stacks, wherein the first resistive material covers the plurality of memory stacks and fails to cover the via;
a first conductive material positioned on the plurality of memory stacks over the first resistive material;
a second resistive material positioned on the first conductive material and the via, wherein the conductive material of the via is in direct contact with the second resistive material; and
a second conductive material positioned on the second resistive material.

13. A memory device, comprising:
a plurality of first access lines extending in a first direction;
respective pluralities of memory stacks on the plurality of first access lines;
a plurality of vias, each aligned in a second direction with a group of memory stacks, each group of memory stacks comprising a memory stack from each of the plurality of first access lines that are aligned in the second direction with the via, each via comprising a conductive material; and
a plurality of second access lines extending in the second direction, each second access line extending over a via of the plurality of vias and the group of memory stacks aligned with the via,
wherein each second access line comprises:
a first resistive material positioned directly on each memory stack of the respective pluralities of memory stacks;
a first conductive material positioned on the first resistive material;
a second resistive material positioned on the via and the first conductive material; and
a second conductive material positioned on the second resistive material.

14. The memory device of claim 13 , wherein the first resistive material does not cover the plurality of vias.

15. The memory device of claim 13 , wherein a resistivity of the first resistive material is greater than a resistivity of the second resistive material.

16. The memory device of claim 13 , wherein each via extends through a dielectric material and a liner material that forms a barrier between the dielectric material and the first resistive material and between the dielectric material and the first conductive material.

17. A memory device, comprising:
a plurality of first access lines extending in a first direction;
respective pluralities of memory stacks on the plurality of first access lines;
a plurality of vias, each aligned in a second direction with a group of memory stacks, each group of memory stacks comprising a memory stack from each of the plurality of first access lines that are aligned in the second direction with the via, each via comprising a conductive material; and
a plurality of second access lines extending in the second direction, each second access line extending over a via of the plurality of vias and the group of memory stacks aligned with the via,
wherein each second access line comprises:
a first resistive material positioned on each memory stack of the respective pluralities of memory stacks;
a first conductive material positioned on the first resistive material;
a second resistive material positioned on the via and the first conductive material, wherein the conductive material of each via is in direct contact with the second resistive material; and
a second conductive material positioned on the second resistive material.

18. The memory device of claim 17 , wherein the first resistive material does not cover the plurality of vias.

19. The memory device of claim 17 , wherein a resistivity of the first resistive material is greater than a resistivity of the second resistive material.

20. The memory device of claim 17 , wherein each via extends through a dielectric material and a liner material that forms a barrier between the dielectric material and the first resistive material and between the dielectric material and the first conductive material.

Assignees

• Micron Technology Inc

Inventors

• Wei Lei
• Zheng Pengyuan
• Baker Kevin Lee
• Ege Efe Sinan
• Barton Adam Thomas
• Venigalla Rajasekhar

Classifications

• H01L45/06

  Electricity · mapped topic

• H01L45/1675

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L27/2481 Primary

  Electricity · mapped topic