Semiconductor device for a low-loss antenna switch

Patent metadata

Field	Value
Publication number	US-11380680-B2
Application number	US-202016874536-A
Country	US
Kind code	B2
Filing date	May 14, 2020
Priority date	Jul 12, 2019
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, first and second wells of a first conductivity type, a third well of a second conductivity type, different from the first conductivity type, a first doped region of the first conductivity type in the second well, a metal-oxide-semiconductor device, and a feature. The metal-oxide-semiconductor device is at least partially disposed within the substrate and includes a gate structure disposed above the first well. The gate structure, the first doped region, or the combination thereof is configured to be floated. The feature is disposed adjacent to the metal-oxide-semiconductor device. The feature extends into the substrate with a first depth and a portion of the metal-oxide-semiconductor device extends into the substrate with a second depth smaller than the first depth.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
first and second wells of a first conductivity type and a third well of a second conductivity type, different from the first conductivity type, wherein the third well is interposed between the first and second wells;
a first doped region of the first conductivity type disposed in the second well;
a metal-oxide-semiconductor device at least partially disposed within the substrate, and comprising:
a gate structure disposed above the first well,
wherein the gate structure, the first doped region, or the combination thereof is configured to be floated; and

a feature disposed adjacent to the metal-oxide-semiconductor device;
wherein the feature extends into the substrate with a first depth and a portion of the metal-oxide-semiconductor device extends into the substrate with a second depth smaller than the first depth.

2. The semiconductor device of claim 1 , wherein the feature comprises:
a plurality of trench isolations each having the first depth ranging from about 0.5 micrometers to about 10 micrometers.

3. The semiconductor device of claim 1 , wherein the feature comprises:
two trench isolations disposed at opposite sides of the metal-oxide-semiconductor device, each has the first depth greater than about 0.5 micrometers.

4. The semiconductor device of claim 1 , further comprising:
a second doped region of the second conductivity type disposed in the third well; and
third to fifth doped regions disposed in the first well, wherein the third to fifth doped regions are included in a structure configured to operate as the metal-oxide-semiconductor device;
wherein the second doped region, the fifth doped region, or the combination thereof is configured to be floated.

5. The semiconductor device of claim 4 , further comprising:
a resistor having a resistance of about 500 ohms to about 1,000,000 ohms,
wherein the fifth doped region is configured to be floated, and the second doped region is coupled to the resistor.

6. The semiconductor device of claim 1 , wherein the substrate has a resistivity ranging from about 100 to about 1,000,000 ohm-cm.

7. The semiconductor device of claim 4 , wherein the third and fourth doped regions are of the second conductivity type.

8. The semiconductor device of claim 4 , wherein the fifth doped region is of the first conductivity type.

9. The semiconductor device of claim 1 , further comprising:
a fourth well of the second conductivity type interposed below the first well.

10. The semiconductor device of claim 9 , wherein the third well is partially interposed between the second well and the fourth well.

11. The semiconductor device of claim 1 , further comprising:
a second doped region of the second conductivity type disposed in the third well; and
a first resistor coupled between the second doped region and a first voltage terminal.

12. The semiconductor device of claim 11 , further comprising:
a second resistor having a first terminal coupled to a second voltage terminal different from the first voltage terminal;
wherein the metal-oxide-semiconductor further comprises:
a third doped region of the first conductivity type disposed in the first well and coupled to a second terminal of the second resistor.

13. A semiconductor device, comprising:
a substrate;
a first well, a second well, and a third well that are disposed within the substrate;
first and second doped regions disposed in a fourth well above the first well, wherein the second well is interposed between the third and fourth wells; and
a third doped region disposed in the third well;
wherein the third doped region is configured to be floated.

14. The semiconductor device of claim 13 , further comprising:
a plurality of resistors; and
a fourth doped region disposed in the fourth well and a fifth doped region disposed in the second well;
wherein the fourth doped region, the fifth doped region, or the combination thereof is configured to be coupled to at least one of the plurality of resistors.

15. The semiconductor device of claim 14 , wherein the plurality of resistors are separated from each other with a predetermined spacing.

16. The semiconductor device of claim 13 , further comprising:
a plurality of metal layers above the substrate; and
at least one resistor disposed above at least one of the plurality of metal layers;
wherein the substrate comprises:
a first portion; and
a second portion arranged between the first portion and the plurality of metal layers, wherein the second portion comprises a material that has a higher impedance than that of the first portion;

wherein the at least one resistor is further disposed above the second portion.

17. The semiconductor device of claim 13 , wherein the first and second doped regions are included in each one of a plurality of metal-oxide-semiconductor devices;
wherein the plurality of metal-oxide-semiconductor devices are separated from each other by a distance which ranges from about 0.001 micrometers to 5 micrometers.

18. A semiconductor device, comprising:
a metal-oxide-semiconductor transistor disposed on a first well of a first conductivity type, wherein the metal-oxide-semiconductor transistor comprises:
a first terminal configured to be as a drain terminal;
a second terminal configured to be as a source terminal, wherein the first and second terminals are coupled to a ground;
a third terminal configured to be a body terminal, wherein the third terminal is coupled to a first resistor that is coupled to the ground;
a fourth terminal coupled to a second resistor that is coupled to a voltage terminal; and
a fifth terminal configured to be floated.

19. The semiconductor device of claim 18 , wherein the metal-oxide-semiconductor transistor comprises:
a first doped region of the first conductivity type and a second doped region of a second conductivity type different from the first conductivity type that are disposed in a second well, of the second conductivity type, created on the first well,
wherein the first doped region corresponds to the second terminal and the second doped region corresponds to the third terminal.

20. The semiconductor device of claim 18 , further comprising:
a second well, of a second conductivity type different from the first conductivity type, arranged adjacent to the first well;
wherein the metal-oxide-semiconductor transistor comprises:
a doped region of the second conductivity type disposed in the second well, wherein the doped region corresponds to the fourth terminal.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Jin Jun-De
• Yeh Tzu-Jin

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D62/116 Primary

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title