Method of erasing data in nonvolatile memory device, nonvolatile memory device performing the same and memory controller performing the same

Patent metadata

Field	Value
Publication number	US-11380403-B2
Application number	US-202117199062-A
Country	US
Kind code	B2
Filing date	Mar 11, 2021
Priority date	Jul 10, 2020
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

In a method of erasing data in a nonvolatile memory device including one or more memory blocks, a plurality of memory cells are disposed in a vertical direction in each memory block. An erase loop is performed once or more on an entire of a first memory block in the one or more memory blocks. After the erase loop is successfully completed, a first partial verification operation is performed on one or more groups of a plurality of groups in the first memory block. After the first partial verification operation is successfully completed, it is determined whether a second partial verification operation is required for a group of the one or more groups. The second partial verification operation is performed on one or more subgroups of a plurality of subgroups in a first group requiring the second partial verification operation among the plurality of groups.

First claim

What is claimed is:

1. A method of erasing data in a nonvolatile memory device including one or more memory blocks, a plurality of memory cells being disposed in a vertical direction in each memory block, the method comprising:
performing an erase loop once or more on an entire of a first memory block in the one or more memory blocks, the erase loop including an erase operation and an erase verification operation;
after the erase loop is successfully completed, performing a first partial verification operation on one or more groups of a plurality of groups in the first memory block, the first memory block being divided into the plurality of groups;
after the first partial verification operation is successfully completed, determining whether a second partial verification operation is required for a group of the one or more groups; and
performing the second partial verification operation on one or more subgroups of a plurality of subgroups in a first group requiring the second partial verification operation among the plurality of groups, the first group being divided into the plurality of subgroups.

2. The method of claim 1 , wherein performing the first partial verification operation on one or more groups of the plurality of groups includes:
detecting a first cell number of the first group based on an erase state of memory cells included in the first group and an erase verification voltage having a second verification level that is different from an erase verification voltage having a first verification level used in the erase verification operation of the erase loop; and
performing the first partial verification operation on the first group based on the first cell number and a first reference number.

3. The method of claim 2 , wherein performing the first partial verification operation on the first group includes:
when the first cell number is less than or equal to the first reference number, determining that the first partial verification operation for the first group is successful; and
when the first cell number is greater than the first reference number, determining that the first partial verification operation for the first group has failed.

4. The method of claim 3 , wherein, when it is determined that the first partial verification operation has failed, the first memory block is indicated as a bad block.

5. The method of claim 2 , wherein:
the plurality of memory cells included in the first memory block are connected to a plurality of wordlines, and
the memory cells included in the first group are connected to M wordlines among the plurality of wordlines, where M is a natural number greater than or equal to two.

6. The method of claim 2 , wherein the first cell number represents a number of memory cells in which a level of a threshold voltage is higher than the second verification level among the memory cells included in the first group.

7. The method of claim 2 , wherein the second verification level is lower than the first verification level.

8. The method of claim 2 , wherein determining whether the second partial verification operation is required for a group of the one or more groups includes:
determining whether the second partial verification operation is required for the first group based on the first cell number and a second reference number.

9. The method of claim 8 , wherein determining whether the second partial verification operation is required for the first group includes:
when the first cell number is greater than the second reference number, determining that the second partial verification operation for the first group is necessary; and
when the first cell number is less than or equal to the second reference number, determining that the second partial verification operation for the first group is unnecessary.

10. The method of claim 8 , wherein the second reference number is less than or equal to the first reference number.

11. The method of claim 8 , wherein performing the second partial verification operation on one or more subgroups of the plurality of subgroups in the first group includes:
when it is determined that the second partial verification operation for the first group is required, detecting a second cell number of a first subgroup of the plurality of subgroups in the first group based on an erase state of memory cells included in the first subgroup and an erase verification voltage having a third verification level that is different from the first verification level; and
performing the second partial verification operation on the first subgroup based on the second cell number and a third reference number that is different from the first and second reference numbers.

12. The method of claim 11 , wherein performing the second partial verification operation on the first subgroup includes:
when the second cell number is less than or equal to the third reference number, determining that the second partial verification operation for the first subgroup is successful; and
when the second cell number is greater than the third reference number, determining that the second partial verification operation for the first subgroup has failed.

13. The method of claim 12 , wherein, when it is determined that the second partial verification operation has failed, the first memory block is indicated as a bad block.

14. The method of claim 11 , wherein:
the memory cells included in the first group are connected to M wordlines, where M is a natural number greater than or equal to two, and
the memory cells included in the first subgroup are connected to N wordlines, where N is a natural number greater than or equal to one and less than M.

15. The method of claim 11 , wherein the second cell number represents a number of memory cells in which a level of a threshold voltage is higher than the third verification level among the memory cells included in the first subgroup.

16. The method of claim 11 , wherein the third verification level is lower than or equal to the second verification level.

17. The method of claim 11 , wherein the third reference number is less than the first and second reference numbers.

18. The method of claim 1 , wherein:
the plurality of groups include first through X-th groups, where X is a natural number greater than or equal to two,
the first partial verification operation and an operation of determining whether the second partial verification operation is required are sequentially performed on each of the first through X-th groups, and
the second partial verification operation is sequentially performed only on one or more groups requiring the second partial verification operation among the first through X-th groups.

19. A nonvolatile memory device comprising:
a memory block including a plurality of memory cells disposed in a vertical direction; and
a control circuit configured to:
perform an erase loop once or more on an entire of the memory block,
perform a first partial verification operation on one or more groups of a plurality of groups in the memory block,
determine whether a second partial verification operation is required for a group of the one or more groups, and
perform the second partial verification operation on one or more subgroups of a plurality of subgroups in a group requiring the second partial verification operation among the plurality of groups,
wherein the erase loop includes an erase operation and an erase verification operation,
wherein the memory block is divided into the plurality of groups, and
wherein the group requiring the second p

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Sunkyu
• Jung Wontaeck

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title