Structure and methodology for detecting defects during MEMS device production

Patent metadata

Field	Value
Publication number	US-11377348-B2
Application number	US-202117166527-A
Country	US
Kind code	B2
Filing date	Feb 3, 2021
Priority date	Jan 2, 2019
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

A wafer includes a process control monitor (PCM) structure formed on a substrate. The PCM structure includes detection and reference structures. The detection structure includes a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement. The reference structure includes a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material. The insulator material does not overlie the detection structure. Methodology entails measuring a capacitance between the detection structure and the substrate, measuring another capacitance between the reference structure and substrate, and comparing the two capacitances to determine whether defects exist.

First claim

What is claimed is:

1. A method for process control monitoring of a wafer, the wafer including a plurality of microelectromechanical systems (MEMS) devices formed thereon, the method comprising:
measuring a first capacitance value between a first electrically conductive line arrangement of a detection structure and a substrate of the wafer, the detection structure having the first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement;
measuring a second capacitance value between a second electrically conductive line arrangement of a reference structure and the substrate of the wafer, the reference structure including the second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an electrically insulating material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the second electrically insulating material;
computing a capacitance difference between the first and second capacitance values; and
determining that a defect may be present in an oxide layer of the substrate underlying the detection structure in response to the capacitance difference.

2. The method of claim 1 wherein prior to the measuring the first and second capacitance values, the method further comprises:
forming the first and second electrically conductive line arrangements of the detection and reference structures in the first structural layer;
forming the first and second protection layers surrounding the first and second electrically conductive line arrangements;
depositing the electrically insulating material overlying the detection and reference structures;
forming the second structural layer overlying the electrically insulating material; and
removing the electrically insulating material from the detection structure so that the second electrically insulating material does not overlie the detection structure, wherein the removing operation enhances the probability of the defect at the detection structure and the presence of the electrically insulating material and the second structural layer overlying the reference structure decreases the probability of the defect at the reference structure.

3. The method of claim 2 wherein:
the forming the second structural layer comprises forming the MEMS devices in the second structural layer; and
the removing the electrically insulating material comprises removing the electrically insulating material underlying active regions of the MEMS devices.

4. The method of claim 1 wherein the determining comprises:
determining that the defect is not present when the capacitance difference is less than a predetermined threshold;
determining that the defect is present when the capacitance difference is greater than the predetermined threshold; and
when the capacitance difference is greater than the predetermined threshold, determining a significance of the defect in response to an amount at which the capacitance difference exceeds the predetermined threshold.

5. The method of claim 1 wherein each of the first and second electrically conductive line arrangements comprises a first comb structure having first line segments and a second comb structure having second line segments that are interdigitated with the first line segments, and the method further comprises:
measuring a third capacitance value between the first and second comb structures of the detection structure;
measuring a fourth capacitance value between the first and second comb structures of the reference structure;
computing a second capacitance difference between the third and fourth capacitance values; and
determining that an additional defect may be present in the oxide layer of the substrate underlying the detection structure between the interdigitated first and second line segments in response to the second capacitance difference.

6. The method of claim 1 wherein the wafer includes a process control monitor (PCM) structure formed on a substrate of the wafer, the PCM structure including the detection structure and the reference structure, wherein the electrically insulating material does not overlie the detection structure.

Assignees

• Nxp Usa Inc

Inventors

• Liu Lianjun

Classifications

• G01R27/2605

  Measuring capacitance (capacitive sensors G01D5/24) · CPC title

• G01R31/2637

  for testing other individual devices (G01R31/2608 - G01R31/2632, G01R31/27 take precedence) · CPC title

• B81C99/004 Primary

  during manufacturing · CPC title

• G01R31/2831

  Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00) · CPC title