Skew detection and correction for orthogonal differential vector signaling codes

Patent metadata

Field	Value
Publication number	US-11368278-B2
Application number	US-202117165635-A
Country	US
Kind code	B2
Filing date	Feb 2, 2021
Priority date	Jun 11, 2018
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

First claim

I claim:

1. A method comprising:
generating a data output from a plurality of signals received on a plurality of wires of a multi-wire bus;
generating an early-late indication from a transition in the data output responsive to transitions in at least two signals of the plurality of signals, each of the transitions in the at least two signals having corresponding wire-specific transition deltas of a set of wire-specific transition deltas having at least two possible magnitudes;
generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining the early-late indication with the corresponding wire-specific transition delta; and
providing each wire-specific skew control signal to a respective wire-skew control element to adjust wire-specific skew.

2. The method of claim 1 , wherein transitions of two signals of the at least two signals have wire-specific transition deltas of equal magnitude and opposite sign.

3. The method of claim 1 , further comprising identifying a transitional data pattern in the data output.

4. The method of claim 3 , wherein the at least two signals undergoing transition are associated with the identified transitional data pattern.

5. The method of claim 1 , wherein the data output is a sub-channel output of a plurality of sub-channel outputs, each sub-channel output generated by a respective multi-input comparator (MIC) forming a respective linear combination of the plurality of signals.

6. The method of claim 5 , wherein each wire-specific skew control signal is further generated based on a corresponding input coefficient of the MIC.

7. The method of claim 6 , wherein at least two input coefficients of the MIC are different.

8. The method of claim 1 , wherein providing each wire-specific skew control signal to a respective wire-skew control element comprises conveying each wire-specific skew control signal to a transmitter generating the plurality of signals on the multi-wire bus.

9. The method of claim 1 , wherein each signal of the plurality of signals has a signal value selected from the group consisting of: [±1, ±⅓].

10. The method of claim 1 , wherein the early-late indication is generated at an output of a sampler applying a speculative decision feedback equalization (DFE) factor to the data output.

11. An apparatus comprising:
a comparator configured to generate a data output from a plurality of signals received on a plurality of wires of a multi-wire bus;
a clock-data-alignment circuit configured to generate an early-late indication from a transition in the data output responsive to transitions in at least two signals of the plurality of signals, each of the transitions in the at least two signals having corresponding wire-specific transition deltas of a set of wire-specific transition deltas having at least two possible magnitudes;
a skew control circuit configured to generate a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining the early-late indication with the corresponding wire-specific transition delta; and
a plurality of wire-skew control elements, each wire-skew control element configured to receive a respective wire-specific skew control signal to adjust wire-specific skew.

12. The apparatus of claim 11 , wherein transitions of two signals of the at least two signals have wire-specific transition deltas of equal magnitude and opposite sign.

13. The apparatus of claim 11 , further comprising a pattern detection circuit configured to identify a transitional data pattern in the data output.

14. The method of claim 13 , wherein the skew control circuit is configured to identify the at least two signals of the plurality of signals undergoing transitions based on the identified transitional data pattern in the data output.

15. The apparatus of claim 11 , wherein the comparator is a multi-input comparator (MIC) configured to form a respective linear combination of the plurality of signals according to a sub-channel vector of a plurality of mutually-orthogonal sub-channel vectors.

16. The apparatus of claim 15 , wherein the skew control circuit is further configured to generate each wire-specific skew control signal based on a corresponding element of the sub-channel vector.

17. The apparatus of claim 16 , wherein the sub-channel vector comprises at least two elements having different magnitude.

18. The apparatus of claim 11 , wherein the plurality of wire-skew control elements are located in a transmitter generating the plurality of signals on the multi-wire bus.

19. The apparatus of claim 11 , wherein each signal of the plurality of signals has a signal value selected from the group consisting of: [±1, ±⅓].

20. The apparatus of claim 11 , wherein the clock-data-alignment circuit comprises a sampler configured to generate the early-late indication, the sampler applying a speculative decision feedback equalization (DFE) factor to the data output.

Assignees

• Kandou Labs SA

Inventors

• Hormati Ali

Classifications

• H04L25/0292 Primary

  Arrangements specific to the receiver end · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H03M7/20

  Conversion to or from n-out-of-m codes · CPC title

• H04L25/0274

  Arrangements for ensuring balanced coupling · CPC title

• H04L25/14

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title