Skew adjustment circuit and skew adjustment method

Patent metadata

Field	Value
Publication number	US-2016134267-A1
Application number	US-201514937247-A
Country	US
Kind code	A1
Filing date	Nov 10, 2015
Priority date	Nov 10, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

A skew adjustment circuit comprises a phase adjustment circuit that adjusts a phase of a first input clock based on a predetermined phase control signal, and outputs it as an output clock, a logical circuit that performs a logical operation between signals that are input, an integral circuit that generates a predetermined voltage signal, based on a result of the logical operation by the logical circuit, a comparator that compares an electric potential of the predetermined voltage signal and an electric potential of a predetermined reference voltage signal, a first controller that generates the predetermined phase control signal based on a result of the comparison by the comparator, and a second controller that performs control for selecting a signal that is to be input to the logical circuit. The second controller, in a first mode, performs the control such that the output clock and a second input clock are selected.

First claim

What is claimed is:

1 . A skew adjustment circuit comprising:
a phase adjustment circuit that adjusts a phase of a first input clock based on a predetermined phase control signal, and outputs the adjusted first input clock as an output clock; a logical circuit that performs a logical operation between signals that are input; an integral circuit that generates a predetermined voltage signal based on a result of the logical operation by the logical circuit; a comparator that compares an electric potential of the predetermined voltage signal and an electric potential of a predetermined reference voltage signal; a phase adjustment amount controller that generates the predetermined phase control signal based on a result of the comparison by the comparator; and a controller that performs control to select a signal to be input to the logical circuit, wherein the controller, in a first mode, performs control such that the output clock and a second input clock are selected.

2 . The skew adjustment circuit according to claim 1 , wherein the logical circuit performs a logical product between the signals that are input.

3 . The skew adjustment circuit according to claim 1 ,
wherein the skew adjustment circuit further comprises a voltage controller that generates the predetermined reference voltage signal based on the result of the comparison, the controller, in a second mode, performs control such that the first input clock is selected, and the voltage controller performs control so as to raise the electric potential of the predetermined reference voltage signal by a predetermined value when the result of the comparison indicates that the electric potential of the predetermined voltage signal is greater than the electric potential of the predetermined reference voltage signal, and to hold the electric potential of the predetermined reference voltage signal when the result of the comparison indicates that the electric potential of the predetermined voltage signal is not greater than the electric potential of the predetermined reference voltage signal.

4 . The skew adjustment circuit according to claim 1 ,
wherein the phase adjustment amount controller performs control so as to raise an electric potential of the predetermined phase control signal by a predetermined value when the result of the comparison indicates that the electric potential of the predetermined voltage signal is greater than the electric potential of the predetermined reference voltage signal, and to hold the electric potential of the predetermined phase control signal when the result of the comparison indicates that the electric potential of the predetermined voltage signal is not greater than the electric potential of the predetermined reference voltage signal.

5 . A multiphase skew adjustment circuit comprising a plurality of skew adjustment circuits each of which adjusts a skew between multiphase clocks, the multiphase clocks having a predetermined phase difference from each other,
wherein each of the plurality of skew adjustment circuits comprises: a first input terminal; a second input terminal; an output terminal; a phase adjustment circuit that adjusts a phase of a first input clock that is input to the first input terminal based on a predetermined comparison signal, and outputs the adjusted first input clock from the output terminal as an output clock; a logical circuit that performs a logical operation between the output clock and a second input clock that is input to the second input terminal; an integral circuit that generates a predetermined voltage signal based on a result of the logical operation by the logical circuit; a comparator that compares an electric potential of the predetermined voltage signal and an electric potential of a predetermined reference voltage signal; and a phase adjustment amount controller that generates the predetermined phase control signal based on a result of the comparison by the comparator, wherein one skew adjustment circuit is configured to receive, through the first input terminal, the first input clock having a predetermined phase difference relative to a first input clock that is input to the first input terminal of the skew adjustment circuit at the previous stage, and to receive, through the second input terminal, the output clock that is output from the output terminal of the skew adjustment circuit at the subsequent stage.

6 . The multiphase skew adjustment circuit according to claim 5 , wherein the logical circuit performs a logical product between the output clock and the second input clock that is input to the second input terminal.

7 . The multiphase skew adjustment circuit according to claim 5 , wherein the skew adjustment circuit at the last stage of the plurality of skew adjustment circuits is configured to receive, through the second input terminal, the output clock that is output from the output terminal of the skew adjustment circuit at the first stage.

8 . A multiphase skew adjustment circuit comprising a plurality of skew adjustment circuits, each of which adjusts a skew between multiphase clocks, the multiphase clocks having a predetermined phase difference from each other,
wherein each of the plurality of skew adjustment circuits comprises: a first input terminal; a second input terminal; an output terminal; a phase adjustment circuit that adjusts a phase of a first input clock that is input to the first input terminal based on a predetermined comparison signal, and outputs the adjusted first input clock from the output terminal as an output clock; a logical circuit that performs a logical operation between the output clock and a second input clock that is input to the second input terminal; an integral circuit that generates a predetermined voltage signal, based on a result of the logical operation by the logical circuit; a comparator that compares an electric potential of the predetermined voltage signal and an electric potential of a predetermined reference voltage signal; and a phase adjustment amount controller that generates the predetermined phase control signal, based on a result of the comparison by the comparator, wherein one skew adjustment circuit receives, through the first input terminal, the first input clock having a predetermined phase difference relative to a first input clock that is input to the first input terminal of the skew adjustment circuit at the previous stage, and receives, through the second input terminal, the output clock that is output from the output terminal of the skew adjustment circuit at the previous stage.

9 . The multiphase skew adjustment circuit according to claim 8 , wherein the logical circuit performs a logical product between the output clock and the second input clock that is input to the second input terminal.

10 . The multiphase skew adjustment circuit according to claim 8 , wherein the multiphase skew adjustment circuit is configured such that a desired electric potential is input to the second input terminal of the skew adjustment circuit at the first stage that is the one skew adjustment circuit.

11 . A method for adjusting a skew between multiphase clocks in a multiphase skew adjustment circuit comprising a plurality of skew adjustment circuits that are connected in a multistage manner, the method comprising:
adjusting a skew between an output clock that is output from a skew adjustment circuit performing a skew adjustment and an output clock from another skew adjustment circuit that is input to the skew adjustment circuit, wherein the adjusting the skew includes: first adjusting a skew between an output clock that is output from the skew adjustment circuit at the l

Assignees

• Megachips Corp

Inventors

• Adachi Shingo

Classifications

• H03K5/159 Primary

  Applications of delay lines not covered by the preceding subgroups · CPC title

• H03K5/156 Primary

  Arrangements in which a continuous pulse train is transformed into a train having a desired pattern · CPC title