Impedance calibration circuit and method of calibrating impedance in memory device

Patent metadata

Field	Value
Publication number	US-11367471-B2
Application number	US-202117352527-A
Country	US
Kind code	B2
Filing date	Jun 21, 2021
Priority date	Nov 11, 2020
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.

First claim

What is claimed is:

1. An impedance calibration circuit included in a memory device comprising:
a first variable impedance circuit connected to a ZQ terminal;
a second variable impedance circuit and a third variable impedance circuit connected to a first node;
a first comparator configured to compare one of a voltage at the ZQ terminal and a voltage at the first node with a reference voltage;
a second comparator configured to compare the voltage at the first node with the reference voltage;
a first control circuit configured to perform a first impedance calibration operation on the first variable impedance circuit based on an output signal from an output of the first comparator;
a second control circuit configured to perform a second impedance calibration operation on the third variable impedance circuit based on an output signal from an output of the second comparator;
a first switch circuit configured to connect an input of the first comparator to one of the ZQ terminal and the first node;
a second switch circuit configured to connect the output of the first comparator to one of the first control circuit and the second control circuit; and
a third switch circuit configured to connect an output of the first switch circuit to one of a first input terminal and a second input terminal of the first comparator and connect the reference voltage to the other.

2. The impedance calibration circuit of claim 1 , wherein:
the first comparator and the first control circuit are configured to perform the first impedance calibration operation on the first variable impedance circuit, and
the second comparator and the second control circuit are configured to perform the second impedance calibration operation on the third variable impedance circuit.

3. The impedance calibration circuit of claim 2 ,
wherein the first impedance calibration operation and the second impedance calibration operation are simultaneously performed.

4. The impedance calibration circuit of claim 2 ,
wherein, the first switch circuit, the second switch circuit, and the third switch circuit are configured to operate such that when the first impedance calibration operation is performed, a second node corresponding to the input of the first comparator is connected to the ZQ terminal using the first switch circuit, the output of the first comparator is connected to the first control circuit using the second switch circuit, and the first input terminal of the first comparator is connected to the reference voltage and the second input terminal of the first comparator is connected to the second node using the third switch circuit.

5. The impedance calibration circuit of claim 2 ,
wherein the first comparator and the second control circuit are configured to perform, after the first impedance calibration operation and the second impedance calibration operation are completed, a third impedance calibration operation on the third variable impedance circuit.

6. The impedance calibration circuit of claim 5 ,
wherein the first switch circuit, the second switch circuit, and the third switch circuit are configured to operate such that, when the third impedance calibration operation is performed, a second node corresponding to the input of the first comparator is connected to the first node using the first switch circuit, the output of the first comparator is connected to the second control circuit using the second switch circuit, and the first input terminal of the first comparator is connected to the reference voltage and the second input terminal of the first comparator is connected to the second node using the third switch circuit.

7. The impedance calibration circuit of claim 6 ,
wherein the second switch circuit includes:
an inverter configured to:
invert the output of the first comparator; and
provide an inverted output of the first comparator to the second control circuit.

8. The impedance calibration circuit of claim 6 , further comprising:
a fourth switch circuit configured to:
during a time when the first impedance calibration operation is performed, connect the output of the second comparator to the second control circuit; and
during a time when the third impedance calibration operation is performed, disconnect the connection between the output of the second comparator and the second control circuit from each other.

9. The impedance calibration circuit of claim 5 ,
wherein the first comparator and the first control circuit are configured to perform, after the third impedance calibration operation is completed, a fourth impedance calibration operation on the first variable impedance circuit.

10. The impedance calibration circuit of claim 9 ,
wherein the first switch circuit, the second switch circuit, and the third switch circuit are configured to operate such that, when the fourth impedance calibration operation is performed, a second node corresponding to the input of the first comparator is connected to the ZQ terminal using the first switch circuit, the output of the first comparator is connected to the first control circuit using the second switch circuit, and the first input terminal of the first comparator is connected to the second node and the second input terminal of the first comparator is connected to the reference voltage using the third switch circuit.

11. The impedance calibration circuit of claim 10 ,
wherein the first control circuit includes:
a first storage circuit configured to store a first impedance calibration code corresponding to a result of the first impedance calibration operation;
a second storage circuit configured to store a second impedance calibration code corresponding to a result of the fourth impedance calibration operation; and
an averaging circuit configured to generate a final impedance calibration code by averaging the first impedance calibration code and the second impedance calibration code.

12. The impedance calibration circuit of claim 9 , wherein:
during a time when an impedance calibration enable signal is activated, the first impedance calibration operation and the second impedance calibration operation are simultaneously performed, and
during a time when the impedance calibration enable signal is activated, the third impedance calibration operation and the fourth impedance calibration operation are sequentially performed after the first impedance calibration operation and the second impedance calibration operation are completed.

13. The impedance calibration circuit of claim 1 , wherein:
the first variable impedance circuit is a first pull-up circuit connected between a power supply voltage and the ZQ terminal,
the second variable impedance circuit is a second pull-up circuit connected between the power supply voltage and the first node, and
the third variable impedance circuit is a pull-down circuit connected between the first node and a ground voltage.

14. The impedance calibration circuit of claim 13 ,
wherein the first pull-up circuit includes:
a plurality of transistors connected in parallel between the power supply voltage and the ZQ terminal.

15. The impedance calibration circuit of claim 1 , wherein:
the first variable impedance circuit is a first pull-down circuit connected between the ZQ terminal and a ground voltage,
the second variable impedance circuit is a second pull-down circuit connected between the first node and the ground voltage,
the third variable impedance circuit is a pull-up circuit connected between a power supply voltage and the first node.

16. A method of calibrating impedance using an impedance calibration circuit t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kavala Anil
• Kim Tongsung
• Yoon Chiweon
• Jeong Byunghoon

Classifications

• G11C29/50008

  of impedance · CPC title

• G11C29/028 Primary

  with adaption or trimming of parameters · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G11C7/1057 Primary

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title