Solid-state imaging device

US11362129B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11362129-B2
Application numberUS-201916561947-A
CountryUS
Kind codeB2
Filing dateSep 5, 2019
Priority dateFeb 27, 2019
Publication dateJun 14, 2022
Grant dateJun 14, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A solid-state imaging device of an embodiment includes plural first transfer gate electrodes, plural second transfer gate electrodes, and plural fixed gate electrodes. The first transfer gate electrodes are such that the respective first transfer gate electrodes are placed in a charge transfer unit to correspond to single light receiving sections, and a control signal ϕ1 is applied. The second transfer gate electrodes are such that the respective second transfer gate electrodes are placed in a charge transfer unit to correspond to the single light receiving sections, and a control signal ϕ2 that differs in phase from the control signal ϕ1 for transferring plural charges is applied. The respective fixed gate electrodes are such that the respective fixed gate electrodes are placed between the first and the second transfer gate electrodes corresponding to the single light receiving sections in the charge transfer unit, and a fixed voltage is applied.

First claim

Opening claim text (preview).

What is claimed is: 1. A solid-state imaging device including a plurality of light receiving sections, and a charge transfer unit configured to transfer a plurality of charges that are generated in the plurality of light receiving sections, comprising: a plurality of first transfer gate electrodes with the respective first transfer gate electrodes placed in the charge transfer unit to correspond to single of the light receiving sections, and a first control signal applied; a plurality of second transfer gate electrodes with the respective second transfer gate electrodes placed in the charge transfer unit to correspond to the single light receiving sections, and a second control signal different in phase from the first control signal applied; a plurality of first fixed gate electrodes with the respective first fixed gate electrodes placed between the respective first transfer gate electrodes and the respective second transfer gate electrodes corresponding to the single light receiving sections in the charge transfer unit, and a first fixed voltage applied; a plurality of storage sections with the respective storage, sections placed adjacently to the single light receiving sections, configured to accumulate the plurality of charges generated in the plurality of light receiving sections; a plurality of shift sections provided between the plurality of storage sections and the charge transfer unit, and configured to shift the plurality of charges of the plurality of storage sections to the charge transfer unit; a plurality of third transfer gate electrodes with the respective third transfer gate electrodes provided to correspond to the respective storage sections, and a third control signal applied; and a plurality of second fixed gate electrodes with the respective second fixed gate electrodes provided to correspond to the respective storage sections, and a second fixed voltage applied. 2. The solid-state imaging device according to claim 1 , wherein a potential wider the respective first fixed gate electrodes is deeper than a potential under the respective first transfer gate electrodes to which the first control signal which is low is applied, and is shallower than a potential under the respective second transfer gate electrodes to which the second control signal which is high being applied. 3. The solid-state imaging device according to claim 2 , wherein the potential under the respective first fixed gate electrodes is specified by ion implantation into an impurity diffusion region under the respective first fixed gate electrodes, or the first fixed voltage that is applied. 4. The solid-state imaging device according to claim 3 , wherein the potential under the respective first transfer gate electrodes and a potential under the respective second transfer gate electrodes are specified by ion implantation into impurity diffusion regions under the respective first transfer gate electrodes and the respective second transfer gate electrodes. 5. The solid-state imaging device according to claim 1 , further comprising: a plurality of shift sections provided between the plurality of light receiving sections and the charge transfer unit, and configured to shift the plurality of charges to the charge transfer unit from the plurality of light receiving sections. 6. The solid-state imaging device according to claim 1 , comprising: a plurality of shift gate electrodes provided in the plurality of shift sections, and a fourth control signal applied, wherein a potential under the respective shift gate electrodes to which the fourth control signal which is high being applied is deeper than a potential under the respective third transfer gate electrodes to which the third control signal which is low is applied, and shallower than the potential under the second transfer gate electrode of the charge transfer unit to which the second control signal which is high is applied. 7. The solid-state imaging device according to claim 1 , wherein the solid-state imaging device is a linear image sensor. 8. A solid-state imaging device including a plurality of light receiving sections, and a charge transfer unit configured to transfer a plurality of charges that are generated in the plurality of light receiving sections, comprising: a plurality of storage sections with the respective storage sections placed adjacently to the light receiving sections, configured to accumulate the plurality of charges generated in the plurality of light receiving sections; a plurality of shift sections provided between the plurality of storage sections and the charge transfer unit, and configured to shift the plurality of charges of the plurality of storage sections to the charge transfer unit; a plurality of first transfer gate electrodes with the respective first transfer gate electrodes provided to correspond to the respective storage sections, and a first control signal applied; a plurality of fixed gate electrodes with the respective fixed gate electrodes provided to correspond to the respective storage sections, and a fixed voltage applied; and a plurality of shift gate electrodes provided in the plurality of shift sections, and a second control signal applied, wherein a potential under the respective shift gate electrodes to which the second control signal which is high being applied is deeper than a potential under the respective first transfer gate electrodes to which the first control signal which is low being applied, and shallower than the potential under a second transfer gate electrode of the charge transfer unit to which the second control signal which is high being applied. 9. The solid-state imaging device according to claim 8 , wherein the solid-state imaging device is a linear image sensor.

Assignees

Inventors

Classifications

  • Transfer or readout registers; Split readout registers or multiple readout registers · CPC title

  • Line sensors · CPC title

  • One-dimensional array CCD image sensors · CPC title

  • Geometry or disposition of pixel elements, address lines or gate electrodes · CPC title

  • H10F39/812Primary

    Arrangements for transferring the charges in the image sensor perpendicular to the imaging plane, e.g. buried regions used to transfer generated charges to circuitry under the photosensitive region · CPC title

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What does patent US11362129B2 cover?
A solid-state imaging device of an embodiment includes plural first transfer gate electrodes, plural second transfer gate electrodes, and plural fixed gate electrodes. The first transfer gate electrodes are such that the respective first transfer gate electrodes are placed in a charge transfer unit to correspond to single light receiving sections, and a control signal ϕ1 is applied. The second …
Who is the assignee on this patent?
Toshiba Kk, Toshiba Electronic Devices & Storage Corp
What technology area does this patent fall under?
Primary CPC classification H10F39/812. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 14 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).