Pseudo-triple-port SRAM bitcell architecture

Patent metadata

Field	Value
Publication number	US-11361817-B2
Application number	US-202017002082-A
Country	US
Kind code	B2
Filing date	Aug 25, 2020
Priority date	Aug 25, 2020
Publication date	Jun 14, 2022
Grant date	Jun 14, 2022

Abstract

A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

First claim

What is claimed is:

1. A memory, comprising:
a semiconductor substrate;
a bitcell arranged on the semiconductor substrate, the bitcell having a bitcell width and a bitcell height and including a first access transistor and a second access transistor;
a first metal layer adjacent the semiconductor substrate, the first metal layer being patterned to form a pair of local bit lines arranged within the bitcell width; the pair of local bit lines including a local bit line coupled to a terminal of the first access transistor and including a complement local bit line coupled to a terminal of the second access transistor;
a second metal layer adjacent the first metal layer; and
a third metal layer adjacent the second metal layer, the third metal layer being patterned to form a first pair of word lines arranged within the bitcell height, the pair of word lines including a first read port word line coupled to a gate of the first access transistor and including a second read port word line coupled to a gate of the second access transistor.

2. The memory of claim 1 , further comprising:
a fourth metal layer adjacent the third metal layer, the fourth metal layer being patterned into a second pair of word lines arranged within the bitcell height, the second pair of word lines including an extra first read port word line coupled to the gate of the first access transistor and an extra second read port word line coupled to the gate of the second access transistor.

3. The memory of claim 2 , further comprising:
a fifth metal layer adjacent the fourth metal layer, the fifth metal layer being patterned into a pair of global bit lines arranged within the bitcell height.

4. The memory of claim 3 , wherein the pair of global bit lines comprises a first read port global bit line and a second read port global bit line.

5. The memory of claim 4 , wherein the fifth metal layer is further patterned into a ground lead, the ground lead being arranged between the first read port global bit line and the second read port global bit line.

6. The memory of claim 4 , wherein the fifth metal layer is further patterned into a power supply voltage lead, the power supply voltage lead being arranged between the first read port global bit line and the second read port global bit line.

7. The memory of claim 3 , wherein the pair of global bit lines comprises a global write bit line and a complement global write bit line.

8. The memory of claim 7 , wherein the fifth metal layer is further patterned into a ground lead, the ground lead being arranged between the global write bit line and the complement global write bit line.

9. The memory of claim 7 , wherein the fifth metal layer is further patterned into a power supply voltage lead, the power supply voltage lead being arranged between the global write bit line and the complement global write bit line.

10. The memory of claim 1 , wherein the first metal layer is further patterned into a power supply voltage lead, the power supply voltage lead being arranged between the local bit line and the complement local bit line.

11. The memory of claim 1 , wherein the memory is included within a cellular telephone.

12. A method, comprising:
forming a bitcell arranged on a semiconductor substrate, the bitcell having a bitcell width and a bitcell height and including a first access transistor and a second access transistor;
patterning a first metal layer adjacent the semiconductor substrate to form a pair of local bit lines arranged within the bitcell width, the pair of local bit lines including a local bit line coupled to a terminal of the first access transistor and including a complement local bit line coupled to a terminal of the second access transistor; and
patterning a third metal layer adjacent to a second metal layer that is adjacent to the first metal layer to form a pair of word lines arranged within the bitcell height, the pair of word lines including a first read port word line coupled to a gate of the first access transistor and including a second read port word line coupled to a gate of the second access transistor.

13. The method of claim 12 , further comprising:
patterning a fourth metal layer adjacent the third metal layer into an extra pair of word lines arranged within the bitcell height, the extra pair of word lines including an extra first read port word line coupled to the gate of the first access transistor and an extra second read port word line coupled to the gate of the second access transistor.

14. The method of claim 13 , further comprising:
patterning a fifth metal layer adjacent the fourth metal layer into a pair of global bit lines arranged within the bitcell height.

15. A memory, comprising:
a semiconductor substrate;
a bitcell arranged on the semiconductor substrate, the bitcell having a bitcell width and a bitcell height and including a first access transistor and a second access transistor;
a first metal layer adjacent the semiconductor substrate, the first metal layer being patterned to form a pair of local bit lines arranged within the bitcell width; the pair of local bit lines including a local bit line coupled to a terminal of the first access transistor and including a complement local bit line coupled to a terminal of the second access transistor;
a second metal layer adjacent the first metal layer;
a third metal layer adjacent the second metal layer, the third metal layer being patterned to form a first pair of global bit lines for the bitcell; and
a fourth metal layer adjacent the third metal layer, the fourth metal layer being patterned to form a pair of word lines arranged within the bitcell height, the pair of word lines including a first read port word line coupled to a gate of the first access transistor and including a second read port word line coupled to a gate of the second access transistor.

16. The memory of claim 15 , wherein the first pair of global bit lines comprises a first read port global bit line and a second read port global bit line.

17. The memory of claim 16 , further comprising:
a fifth metal layer adjacent the fourth metal layer, the fifth metal layer being patterned to form a second pair of global bit lines arranged within the bitcell height.

18. The memory of claim 17 , wherein the second pair of global bit lines comprise a global write bit line and a complement global write bit line.

19. The memory of claim 18 , wherein the fifth metal layer is further patterned into a ground lead arranged between the global write bit line and the complement global write bit line.

20. The memory of claim 18 , wherein the fifth metal layer is further patterned into a power supply voltage lead arranged between the global write bit line and the complement global write bit line.

21. A method, comprising:
forming a bitcell arranged on a semiconductor substrate, the bitcell having a bitcell width and a bitcell height and including a first access transistor and a second access transistor;
patterning a first metal layer adjacent the semiconductor substrate to form a pair of local bit lines arranged within the bitcell width, the pair of local bit lines including a local bit line coupled to a terminal of the first access transistor and including a complement local bit line coupled to a terminal of the second access transistor
patterning a third metal layer adjacent to a second metal layer that is adjacent to the first metal layer to form a first pair of global bit lines for the bitcell; and
patterning a fourth metal layer adjacent the th

Assignees

• Qualcomm Inc

Inventors

• Pallerla Arun Babu
• Jung Changho
• Son Sung
• Cheng Jason
• Gao Yandong
• Jung Chulmin
• Boynapalli Venugopal

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C7/227

  Timing of memory operations based on dummy memory elements or replica circuits · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title