Nanometer scale nonvolatile memory device and method for storing binary and quantum memory states

Patent metadata

Field	Value
Publication number	US-11355697-B2
Application number	US-202017103710-A
Country	US
Kind code	B2
Filing date	Nov 24, 2020
Priority date	Nov 25, 2019
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

Example implementations include an electronic memory device with a metallic layer having a first planar crystalline structure, a first encapsulating layer including an encapsulating material having a second planar crystalline structure, and disposed adjacent to a first planar surface of the metallic layer, and a second encapsulating layer including the encapsulating material, and disposed adjacent to a second planar surface of the metallic layer. Example implementations also include a method of depositing graphite crystals onto a substrate to form a gate bottom layer, depositing BN crystals onto the graphite bottom layer to form a BN bottom layer, depositing tungsten ditelluride (WTe2) crystals onto the BN bottom layer to form a metallic layer, depositing the BN crystals onto the BN bottom layer and the metallic layer to form a BN top layer, and depositing the graphite crystals onto the BN top layer to form a gate top layer.

First claim

What is claimed is:

1. An electronic memory device comprising:
a metallic layer comprising an electronic memory cell and having a first planar crystalline structure;
a first encapsulating layer including an encapsulating material having a second planar crystalline structure, and disposed adjacent to a first planar surface of the metallic layer; and
a second encapsulating layer including the encapsulating material, and disposed adjacent to a second planar surface of the metallic layer.

2. The device of claim 1 , wherein the metallic layer comprises tungsten ditelluride (WTe 2 ).

3. The device of claim 1 , wherein the metallic layer comprises a plurality of stacked crystalline planes.

4. The device of claim 3 , wherein at least one of the plurality of stacked crystalline planes are moveable in a planar direction in response to electrical stimulus.

5. The device of claim 3 , wherein the plurality of stacked crystalline planes comprises an odd number of stacked crystalline planes.

6. The device of claim 1 , wherein a thickness of the metallic layer in a direction perpendicular to a plane of the metallic layer is less than or equal to 5 nm.

7. The device of claim 1 , further comprising:
a first gate layer including a gate material having a third planar crystalline structure, and disposed adjacent to a planar surface of the first encapsulating layer.

8. The device of claim 1 , further comprising:
a second gate layer including the gate material, and disposed adjacent to a planar surface of the second encapsulating layer.

9. The device of claim 1 , further comprising:
a first terminal coupled to a first edge of the metallic layer; and
a second terminal coupled to a second edge of the metallic layer opposite to the first edge.

10. The device of claim 9 , wherein the first terminal and the second terminal are operably coupled to a current source.

11. The device of claim 1 , further comprising:
a third terminal coupled to a third edge of the metallic layer; and
a fourth terminal coupled to a fourth edge of the metallic layer opposite to the third edge.

12. The device of claim 11 , wherein the third terminal and the fourth terminal are operably coupled to a voltage detector.

13. A method of manufacturing an electronic memory device, comprising:
depositing graphite crystals onto a substrate to form a gate bottom layer;
depositing BN crystals onto the graphite bottom layer to form a BN bottom layer;
depositing tungsten ditelluride (WTe 2 ) crystals onto the BN bottom layer to form a metallic layer;
depositing the BN crystals onto the BN bottom layer and the metallic layer to form a BN top layer; and
depositing the graphite crystals onto the BN top layer to form a gate top layer.

14. The method of claim 13 , further comprising:
exfoliating the WTe 2 crystals onto the substrate;
wherein depositing the BN crystals comprises depositing BN crystals having a thickness between 10 nm and 30 nm.

15. The method of claim 13 , further comprising:
exfoliating the boron nitride (BN) crystals onto the substrate,
wherein depositing the BN crystals comprises depositing BN crystals having a thickness between 10 nm and 30 nm.

16. The method of claim 13 , further comprising:
exfoliating the graphite crystals onto the substrate,
wherein depositing the graphite crystals comprises depositing graphite crystals having a thickness between 2 nm and 5 nm.

17. The method of claim 13 , further comprising:
depositing at least one conductive layer on the BN bottom layer to form at least one conductive contact.

18. A method of operating an electronic memory device, the method comprising:
applying an alternating current to a first terminal and a second terminal of an electronic memory device, the electronic memory device including a metallic layer having a first planar crystalline structure, a first encapsulating layer including an encapsulating material having a second planar crystalline structure, and a second encapsulating layer including the encapsulating material;
inducing a Berry dipole at the metallic layer in response to the alternating current; and
detecting the Berry dipole by a voltage detector operatively coupled to a third terminal and a fourth terminal of the electronic device.

19. The method of claim 18 , wherein the inducing the Berry dipole comprises inducing one of a first dipole state, a second dipole state opposite to the first dipole state, and a third dipole state having a neutral dipole state.

20. The method of claim 18 , wherein the inducing the Berry dipole comprises inducing one of a first binary state, a second binary state opposite to the first binary state, and a quantum state distinct from the first binary state and the second binary state.

Assignees

• Univ Leland Stanford Junior

Inventors

• Xiao Jun
• Lindenberg Aaron

Classifications

• H10N52/85

  Materials of the active region · CPC title

• G11C11/56 Primary

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• G11C13/00

  Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 · CPC title

• G11C11/18

  using Hall-effect devices · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title