Thin film transistor and manufacturing method thereof and electronic device

Patent metadata

Field	Value
Publication number	US-11355647-B2
Application number	US-201816331008-A
Country	US
Kind code	B2
Filing date	Aug 17, 2018
Priority date	Oct 25, 2017
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

A thin film transistor includes an active layer, a source electrode and a drain electrode. The active layer includes a conductive region and the conductive region is between the source electrode and the drain electrode and is spaced apart from at least one of the source electrode and the drain electrode.

First claim

What is claimed is:

1. A thin film transistor, comprising an active layer, a source electrode, and a drain electrode,
wherein the active layer comprises a conductive region, and the conductive region is between the source electrode and the drain electrode and is spaced apart from at least one of the source electrode and the drain electrode.
the active layer comprises a concave surface close to a side of the source electrode and the drain electrode, and
the concave surface is at least partially overlapped with the conductive region in a direction perpendicular to a plane in which the active layer is located.

2. The thin film transistor according to claim 1 , wherein the conductive region is spaced apart from both the source electrode and the drain electrode.

3. The thin film transistor according to claim 1 , wherein the conductive region runs through the active layer in a thickness direction of the active layer.

4. An array substrate, comprising the thin film transistor according to claim 1 .

5. The thin film transistor according to claim 1 , wherein the conductive region is a surface portion of the active layer, and
the conductive region does not run through the active layer in a thickness direction of the active layer.

6. The thin film transistor according to claim 1 , wherein the conductive region is directly connected with the source electrode and a channel region is between the conductive region and the drain electrode; or
the conductive region is directly connected with the drain electrode and the channel region is between the conductive region and the source electrode.

7. The thin film transistor according to claim 6 , wherein the conductive region is partially overlapped with the drain electrode or the source electrode in the direction perpendicular to the plane in which the active layer is located.

8. The thin film transistor according to claim 1 , wherein the thin film transistor is in a top-gate structure or a bottom-gate structure.

9. The thin film transistor according to claim 8 , wherein the thin film transistor is in the bottom-gate structure,
the thin film transistor comprises a back channel etching structure, and
the concave surface is a surface of the back channel etching structure.

10. The thin film transistor according to claim 1 , wherein a material of the active layer is a metal oxide semiconductor material, an amorphous silicon material or a polysilicon material.

11. The thin film transistor according to claim 10 , wherein the metal oxide semiconductor material comprises indium gallium zinc oxide, indium zinc oxide, zinc oxide or gallium zinc oxide.

12. An electronic device, comprising the thin film transistor according to claim 1 .

13. The electronic device according to claim 12 , wherein the electronic device is a liquid crystal display device, an organic light emitting diode display device or an e-paper display device.

14. A manufacturing method of a thin film transistor, comprising:
forming an active layer, a source electrode, and a drain electrode; and
performing a conduction treatment on a portion of the active layer to allow the portion to become a conductive region,
wherein the conductive region is formed between the source electrode and the drain electrode and is spaced apart from at least one of the source electrode and the drain electrode,
the active layer comprises a concave surface close to a side of the source electrode and the drain electrode, and
the concave surface is at least partially overlapped with the conductive region in a direction perpendicular to a plane in which the active layer is located.

15. The manufacturing method of the thin film transistor according to claim 14 , wherein the conduction treatment comprises:
forming a mask layer with an opening on the active layer, the opening exposing at least the portion of the active layer; and
performing the conduction treatment on the active layer using the mask layer.

16. The manufacturing method of the thin film transistor according to claim 15 , wherein the opening corresponds to a portion between the source electrode and the drain electrode, and
the source electrode and the drain electrode are both covered by the mask layer.

17. The manufacturing method of the thin film transistor according to claim 15 , wherein the opening exposes only one of the source electrode and the drain electrode.

18. The manufacturing method of the thin film transistor according to claim 15 , wherein a source-drain electrode layer is formed after forming the active layer and before the forming the mask layer, and
the source-drain electrode layer is patterned to form the source electrode and the drain electrode.

19. A manufacturing method of a thin film transistor, comprising:
forming an active layer, a source electrode, and a drain electrode; and
performing a conduction treatment on a portion of the active layer to allow the portion to become a conductive region,
wherein the conductive region is formed between the source electrode and the drain electrode and is spaced apart from at least one of the source electrode and the drain electrode, and the conduction treatment comprises performing a plasma treatment on the active layer.

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Hu Yingbin
• Zhao Ce
• Wang Dongfang
• Zhou Bin
• Liu Jun
• Ding Yuankui
• Li Wei

Classifications

• H10D30/674

  characterised by the active materials · CPC title

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title