CES-based latching circuits

Patent metadata

Field	Value
Publication number	US-11355192-B2
Application number	US-201715710290-A
Country	US
Kind code	B2
Filing date	Sep 20, 2017
Priority date	Feb 23, 2016
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

First claim

The invention claimed is:

1. A device comprising:
latching circuitry, the latching circuitry to comprise:
at least one correlated electron switch (CES) element; and
a control circuit coupled to the at least one CES element, wherein the control circuit to:
receive at least one control signal; and
perform storing input signals or providing output signals, or a combination thereof, based, at least in part, on the at least one CES element and the at least one control signal, wherein the control circuit to comprise a write circuit, wherein the write circuit to:
receive input signals; and
program the at least one CES element into one of a plurality of impedance states to comprise at least a low impedance and/or conductive state and a high impedance and/or insulative state based, at least in part, on the received input signals, the write circuit to comprise a first transistor to couple the at least one CES element to a first voltage supply to apply a first programming signal to the at least one CES element to place the at least one CES element in the low impedance and/or conductive state and a second transistor to couple the at least one CES element to the first voltage supply to apply a second programming signal to the at least one CES element to place the at least one CES element in the high impedance and/or insulative state, wherein:
the first transistor is designed to provide the first programming signal, responsive to an input signal at a first logic level applied to a gate terminal of the first transistor, to impart a first current density in the at least one CES element to establish a threshold current density condition in the at least one CES element for a subsequent transition to the high impedance and/or insulative state responsive to application of the second programming signal; and
the second transistor is designed so that the second programming signal, responsive to the input signal at a second logic level to a gate terminal of the second transistor, to impart a second current density in the at least one CES element to exceed the threshold current density condition in the at least one CES element, and
wherein the write circuit further to comprise a third transistor, wherein:
a first terminal of the third transistor to receive the first voltage supply; and
the third transistor to couple the first voltage supply to the first transistor and/or the second transistor responsive to a write enable signal applied to a gate terminal of the third transistor.

2. The device as claimed in claim 1 , wherein the control circuit to comprise a read circuit, wherein the read circuit to output at least one of the stored input signals based, at least in part, on a current impedance state of the at least one CES element.

3. The device as claimed in claim 1 , wherein the control circuit to comprise a restore circuit, wherein the restore circuit to restore a state of the latching circuitry based, at least in part, on a current impedance state of the at least one CES element.

4. The device as claimed in claim 1 , wherein the write circuit further to:
program the at least one CES element to the low impedance and/or conductive state while the input signal is at the first logic level; and
program the at least one CES element to the high impedance and/or insulative state while the input signal is at the second logic level.

5. The device as claimed in claim 1 , wherein:
a source input of the third transistor to receive the first voltage supply;
a drain input of the first transistor to be coupled to a source input of the second transistor and a drain input of the third transistor;
a drain input of the second transistor to be coupled to a first input of the at least one CES element; and
a drain input of the first transistor to be coupled to the first input of the at least one CES element.

6. The device as claimed in claim 2 , wherein the read circuit to comprise an output node, a fourth transistor, a fifth transistor, and a sixth transistor, wherein:
a drain input of the fourth transistor to receive a second voltage supply;
a gate input of the fourth transistor to receive the at least one control signal;
a source input of the fourth transistor to be connected to the output node;
a drain input of the fifth transistor to be connected to the output node;
a gate input of the fifth transistor to receive the at least one control signal;
a drain input of the sixth transistor to be connected to the source input of the fifth transistor and a first input of the at least one CES element, and wherein a second input of the at least one CES element to be coupled to a third voltage supply;
a gate input of the sixth transistor to receive the at least one control signal; and
a source input of the sixth transistor to be connected to the third voltage supply.

7. The device as claimed in claim 6 , wherein the read circuit further to:
provide a first output at the output node while the at least one CES element is in the low impedance and/or conductive state; and
provide a second output at the output node while the at least one CES element is in the high impedance and/or insulative state.

8. The device as claimed in claim 6 , wherein an impedance value of the fourth transistor and the sixth transistor to be about equal to at least twice an impedance value of the fifth transistor.

9. The device as claimed in claim 4 , wherein:
a drain input of the first transistor to be coupled to a source input of the second transistor, and wherein the drain input of the first transistor to receive the first voltage supply;
a gate input of the first transistor to receive the input signal;
a body input of the first transistor to receive a second voltage supply;
a source input of the first transistor to be coupled to a source input of the third transistor;
the source input of the second transistor to be coupled to the drain input of the first transistor, and wherein the source input of the second transistor to receive the first voltage supply;
a gate input of the second transistor is coupled to the input signal;
a body input of the second transistor to be coupled to the source input of the second transistor;
a drain input of the second transistor to be coupled to the source input of the third transistor;
a body input of the third transistor to receive the first voltage supply; and
a drain input of the third transistor to be coupled to a first input of the at least one CES element, and wherein a second input of the at least one CES element is coupled to a third voltage supply.

10. The device as claimed in claim 2 , wherein the read circuit further to comprise an output node, a fourth transistor and a fifth transistor, wherein:
a drain input of the fourth transistor to receive a second voltage supply;
a gate input of the fourth transistor to receive the at least one control signal;
a source input of the fourth transistor to be connected to the output node;
a drain input of the fifth transistor to be connected to the output node;
a gate input of the fifth transistor to receive the at least one control signal; and
a source input of the fifth transistor to be connected to a first terminal of the at least one CES element, and wherein a second input of the at least one CES element to be coupled to a third voltage supply.

11. The device as claimed in claim 10 , wherein the read circuit to:
provide a first output at the output node while the at least one CES element is in the low impedance and/or conductive state; and
provide a second output at the output node while the at least one CES element is in the high impedance and/or insulative state.

12. The device as claimed in claim 1 ,

Assignees

• Advanced Risc Mach Ltd

Inventors

• Aitken Robert Campbell
• Chandra Vikas
• Sandhu Bal S
• Lattimore George Mcneil
• Das Shidhartha
• Biggs John Philip
• Savanth Parameshwarappa Anand Kumar
• Myers James Edward

Classifications

• G11C14/009 Primary

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title

• H03K3/356008

  ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0007 Primary

  comprising metal oxide memory material, e.g. perovskites · CPC title