Method and apparatus for controlling a computing process

Patent metadata

Field	Value
Publication number	US-11353797-B2
Application number	US-201716463430-A
Country	US
Kind code	B2
Filing date	Nov 24, 2017
Priority date	Dec 9, 2016
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

A method of controlling a computer process for designing or verifying a photolithographic component includes building a source tree including nodes of the process, including dependency relationships among the nodes, defining, for some nodes, at least two different process conditions, expanding the source tree to form an expanded tree, including generating a separate node for each different defined process condition, and duplicating dependent nodes having an input relationship to each generated separate node, determining respective computing hardware requirements for processing the node, selecting computer hardware constraints based on capabilities of the host computing system, determining, based on the requirements and constraints and on dependency relations in the expanded tree, an execution sequence for the computer process, and performing the computer process on the computing system.

First claim

The invention claimed is:

1. A method of controlling a computer process for designing or verifying at least part of a device manufacturing method, the method comprising:
building a source tree comprising a plurality of nodes of the process, including dependency relationships among at least some of the plurality of nodes;
defining, for at least one of the nodes, at least two different process conditions of the device manufacturing method for that at least one node;
expanding the source tree to form an expanded tree, wherein the expanding comprises:
generating, for each of the different process conditions, a separate node for each different defined process condition; and
duplicating, for each generated separate node, one or more dependent nodes having an input relationship to each generated separate node;

determining, for each node in the expanded tree, respective computing hardware requirements for processing the node;
selecting one or more computer hardware constraints based on capabilities of a computing system on which the computer process is to be performed;
determining, based on the determined hardware requirements and on the selected one or more computer hardware constraints and on dependency relationships in the expanded tree, an execution sequence for the computer process; and
performing the computer process on the computing system based on the determined execution sequence.

2. The method as in claim 1 , wherein the one or more computer hardware constraints include processing power and/or memory.

3. The method as in claim 1 , wherein the selecting one or more computer hardware constraints comprises selecting minimizing an amount of memory required to execute the computer process.

4. The method as in claim 1 , wherein the selecting computer one or more hardware constraints comprises selecting minimizing an amount of processing power required to execute the computer process.

5. The method as in claim 1 , wherein the selecting one or more computer hardware constraints comprises selecting an intermediate value between minimizing an amount of memory required to execute the computer process and minimizing an amount of processing power required to execute the computer process.

6. The method as in claim 1 , wherein at least one of the nodes of the process represents one or more inputs selected from: a model, a process window, a focus condition, a layer design, a layer simulation, a detector process, or geometry.

7. The method as in claim 1 , wherein the dependency relationships include input and output relationships.

8. The method as in claim 1 , wherein the determining an execution sequence further comprises:
defining a plurality of time steps for performing the computer process;
assigning each node to a time step; and
assigning each node a life span in time steps.

9. The method as in claim 8 , wherein the life span of each node comprises a number of time steps in which there exists at least one node that has a dependency on that node.

10. A computing system comprising:
a processor; and
a non-transitory machine readable medium comprising instructions for performing the method of claim 1 .

11. A computer program product comprising a non-transitory machine-readable medium having instructions therein, the instructions, upon execution by a computer system, configured to cause the computer system to at least:
build a source tree comprising a plurality of nodes of a computer process for designing or verifying at least part of a device manufacturing method, including dependency relationships among at least some of the plurality of nodes;
define, for at least one of the nodes, at least two different process conditions of the device manufacturing method for that at least one node;
expand the source tree to form an expanded tree, wherein the expansion comprises:
generation, for each of the different process conditions, of a separate node for each different defined process condition; and
duplication, for each generated separate node, of one or more dependent nodes having an input relationship to each generated separate node;

determine, for each node in the expanded tree, respective computing hardware requirements for processing the node;
select one or more computer hardware constraints based on capabilities of a computing system on which the computer process is to be performed;
determine, based on the determined hardware requirements and on the selected one or more computer hardware constraints and on dependency relationships in the expanded tree, an execution sequence for the computer process; and
perform the computer process on the computing system based on the determined execution sequence.

12. The computer program product of claim 11 , wherein the one or more computer hardware constraints include processing power and/or memory.

13. The computer program product of claim 11 , wherein the selection of one or more computer hardware constraints comprises selection of minimization of an amount of memory required to execute the computer process.

14. The computer program product of claim 11 , wherein the selection of one or more computer hardware constraints comprises selection of minimization of an amount of processing power required to execute the computer process.

15. The computer program product of claim 11 , wherein the selection of one or more computer hardware constraints comprises selection of an intermediate value between minimization of an amount of memory required to execute the computer process and minimization of an amount of processing power required to execute the computer process.

16. The computer program product of claim 11 , wherein at least one of the nodes of the process represents one or more inputs selected from: a model, a process window, a focus condition, a layer design, a layer simulation, a detector process, or geometry.

17. The computer program product of claim 11 , wherein the dependency relationships include input and output relationships.

18. The computer program product of claim 11 , wherein instructions configured to cause the determination of an execution sequence is further configured to cause the computer system to:
define a plurality of time steps for performing the computer process;
assign each node to a time step; and
assign each node a life span in time steps.

19. The computer program product of claim 18 , wherein the life span of each node comprises a number of time steps in which there exists at least one node that has a dependency on that node.

20. The computer program product of claim 11 , wherein the device manufacturing process comprises a lithographic projection step.

Assignees

• Asml Netherlands Bv

Inventors

• Lu Yen-Wen
• Chen Xiaorui
• Lin Yang

Classifications

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G03F7/70525 Primary

  Controlling normal operating mode, e.g. matching different apparatus, remote control or prediction of failure · CPC title

• G03F7/70483 Primary

  Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring · CPC title

• G05B2219/45031

  Manufacturing semiconductor wafers · CPC title

• G05B19/41875

  characterised by quality surveillance of production · CPC title