High-side gate over-voltage stress testing

Patent metadata

Field	Value
Publication number	US-11353494-B2
Application number	US-202016792671-A
Country	US
Kind code	B2
Filing date	Feb 17, 2020
Priority date	Dec 22, 2016
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

A testing system includes: a substrate having a probe pad and having a supply input; driver circuitry having a driver output; a transistor having a gate, a source, and a drain; and a field effect transistor (FET) engager. The gate of the transistor is coupled to the driver output, and the drain of the transistor is coupled to the supply input. The FET engager is configured to couple the probe pad to the gate of the transistor and provide test instrument measurement of gate current of the transistor without test instrument probe capacitance impacting operation of the transistor.

First claim

What is claimed is:

1. A testing system comprising:
a substrate having a probe pad and having a supply input;
driver circuitry having a driver output;
a transistor having a gate coupled to the driver output, having a source, and having a drain coupled to the supply input;
a field effect transistor engager configured to couple the probe pad to the gate of the transistor and provide test instrument probe measurement of gate current from the transistor without test instrument probe capacitance affecting operation of the transistor.

2. The testing system of claim 1 in which the field effect transistor engager is configured selectively to couple the probe pad to the gate of the transistor in a test mode.

3. The testing system of claim 1 in which the field effect transistor engager is configured selectively to couple the probe pad to the gate of the transistor in a test mode and to selectively uncouple the probe pad from the gate of the transistor in normal operation.

4. The testing system of claim 1 in which the field effect transistor engager is configured to provide a fail-safe against accidental turn-on during normal operation.

5. The testing system of claim 1 in which the probe pad is a first probe pad, and the substrate having a second probe pad configured for a test instrument to turn on the field effect transistor engager in response to an external voltage applied to the second probe pad.

6. The testing system of claim 5 including a test instrument coupled to the second probe pad.

7. The testing system of claim 5 including a first test instrument coupled to the first probe pad and a second test instrument coupled to the second probe pad.

8. The testing system of claim 1 in which the field effect transistor engager is configured to couple the probe pad to the gate of transistor and provide test instrument probe measurement of gate current from the transistor without test instrument probe capacitance affecting operation of the transistor when forcing a source-to-drain voltage of the transistor up to a selected stress voltage.

9. The testing system of claim 1 in which the transistor is a first transistor, and the field effect transistor engager includes a second transistor coupled to the first transistor, and in which the field effect transistor engager is configured to provide an indication of gate current of the first transistor without test instrument capacitance impacting operation of the first transistor in a normal mode of operation different from a test mode in which the second transistor is configured to provide the indication of gate current of the first transistor.

10. The testing system of claim 1 in which the driver circuitry, the transistor, and the field effect transistor engager are formed on the substrate.

11. The testing system of claim 1 in which the transistor and the field effect transistor engager are N-type metal-oxide semiconductor transistors.

12. The testing system of claim 1 including a diode having a cathode coupled to a system ground and having an anode coupled to the source of the field effect transistor engager.

13. The testing system of claim 1 in which the field effect transistor engager has a gate and including a resistor coupled between a system ground and the gate of the field effect transistor engager.

14. The testing system of claim 1 in which the source of the transistor is coupled to a package pin.

15. The testing system of claim 1 including a test instrument coupled to the probe bond pad.

Assignees

• Texas Instruments Inc

Inventors

• Gonzalez Diaz Sigfredo E
• Amey Benjamin Lee
• Teterud Patrick Michael
• Nguyen Hung

Classifications

• G01R31/2623 Primary

  for measuring break-down voltage therefor · CPC title