Wideband buffer with DC level shift and bandwidth extension for wired data communication

Patent metadata

Field	Value
Publication number	US-11349463-B2
Application number	US-202017084494-A
Country	US
Kind code	B2
Filing date	Oct 29, 2020
Priority date	Oct 29, 2020
Publication date	May 31, 2022
Grant date	May 31, 2022

Abstract

A wideband buffer circuit and a wideband communication circuit that uses the wideband buffer circuit. The wideband buffer circuit includes first and second transistors deployed as a voltage buffer and connected to first and second input terminals, first and second parallel resistor-capacitor pairs connected to the first and second transistors, first and second cross-coupled transistors connected to the first and second parallel resistor-capacitor pairs and connected to first and second output terminals, and first and second current sources connected to the first and second cross-coupled transistors and a fixed voltage. The first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series. The second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.

First claim

What is claimed is:

1. A wideband buffer circuit comprising:
first and second transistors deployed as a voltage buffer and connected to first and second input terminals;
first and second parallel resistor-capacitor pairs connected to the first and second transistors;
first and second cross-coupled transistors connected to the first and second parallel resistor-capacitor pairs and connected to first and second output terminals; and
first and second current sources connected to the first and second cross-coupled transistors and a fixed voltage,
wherein the first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series and wherein the second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.

2. The wideband buffer circuit of claim 1 , further comprising a capacitor connected to a first node between the first cross-coupled transistor and the first current source and a second node between the second cross-coupled transistor and the second current source.

3. The wideband buffer circuit of claim 1 , wherein the first output terminal is connected to a first node between the first parallel resistor-capacitor pair and the first cross-coupled transistor and the second output terminal is connected to a second node between the second parallel resistor-capacitor pair and the second cross-coupled transistor.

4. The wideband buffer circuit of claim 1 , wherein the first and second transistors are emitter followers.

5. The wideband buffer circuit of claim 1 , wherein the first and second input terminals are connected to bases or gates of the first and second transistors.

6. The wideband buffer circuit of claim 1 , wherein each of the first and second current sources includes a bipolar transistor and a resistor connected in series to ground.

7. The wideband buffer circuit of claim 1 , wherein each of the first and second current sources includes a metal-oxide-semiconductor (MOS) transistor connected to the fixed voltage.

8. The wideband buffer circuit of claim 1 , wherein further comprising a first resistor connected to a supply voltage and the first transistor and a second resistor connected to the supply voltage and the second transistor.

9. The wideband buffer circuit of claim 1 , further comprising a third current source connected to a first node between the first parallel resistor-capacitor pair and the first cross-coupled transistor and to the fixed voltage and a fourth current source connected to a second node between the second parallel resistor-capacitor pair and the second cross-coupled transistor and to the fixed voltage.

10. A wideband communication circuit comprising:
a wideband buffer with first and second input terminals to receive input signals and first and second output terminals to transmit output signals; and
a continuous-time linear equalizer (CTLE) connected to the first and second output terminals of the wideband buffer to equalize the output signals from the wideband buffer,
wherein the wideband buffer comprises:
first and second transistors deployed as a voltage buffer and connected to the first and second input terminals;
first and second parallel resistor-capacitor pairs connected to the first and second transistors;
first and second cross-coupled transistors connected to the first and second parallel resistor-capacitor pairs and connected to the first and second output terminals; and
first and second current sources connected to the first and second cross-coupled transistors and a fixed voltage,
wherein the first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series and wherein the second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.

11. The wideband communication circuit of claim 10 , wherein the wideband buffer further comprises a capacitor connected to a first node between the first cross-coupled transistor and the first current source and a second node between the second cross-coupled transistor and the second current source.

12. The wideband communication circuit of claim 10 , wherein the first output terminal of the wideband buffer is connected to a first node between the first parallel resistor-capacitor pair and the first cross-coupled transistor and the second output terminal of the wideband buffer is connected to a second node between the second parallel resistor-capacitor pair and the second cross-coupled transistor.

13. The wideband communication circuit of claim 10 , wherein the first and second input terminals of the wideband buffer are connected to bases or gates of the first and second transistors.

14. The wideband communication circuit of claim 10 , wherein the wideband buffer further comprises a first resistor connected to a supply voltage and the first transistor and a second resistor connected to the supply voltage and the second transistor.

15. The wideband communication circuit of claim 10 , wherein the wideband buffer further comprises a third current source connected to a first node between the first parallel resistor-capacitor pair and the first cross-coupled transistor and to the fixed voltage and a fourth current source connected to a second node between the second parallel resistor-capacitor pair and the second cross-coupled transistor and to the fixed voltage.

16. The wideband communication circuit of claim 10 , further comprising a transmitter driver connected to the CTLE, wherein the wideband communication circuit is a redriver.

17. A wideband buffer circuit comprising:
first and second transistors deployed as a voltage buffer and connected to first and second input terminals;
first and second parallel resistor-capacitor pairs connected to the first and second transistors, wherein resistors of the first and second parallel resistor-capacitor pairs provide signal paths for low frequency signals and wherein capacitors of the first and second parallel resistor-capacitor pairs provide signal paths for high frequency signals;
first and second cross-coupled transistors connected to the first and second parallel resistor-capacitor pairs and connected to first and second output terminals;
another capacitor connected to the first and second cross-coupled transistors and the first current source, wherein the another capacitor and the first and second cross-coupled transistors provide negative capacitance for bandwidth expansion; and
first and second current sources connected to the first and second cross-coupled transistors and a fixed voltage,
wherein the first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series and wherein the second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.

18. The wideband buffer circuit of claim 17 , wherein the first output terminal is connected to a first node between the first parallel resistor-capacitor pair and the first cross-coupled transistor and the second output terminal is connected to a second node between the second parallel resistor-capacitor pair and the second cross-coupled transistor.

19. The wideband buffer circuit of claim 17 , wherein further comprising a first resistor connected to a suppl

Assignees

• Nxp Bv

Inventors

• Delshadpour Siamak
• Zhang Xu

Classifications

• H03K19/017509

  Interface arrangements · CPC title

• H03K19/00315 Primary

  in field-effect transistor circuits · CPC title

• H03K5/2436

  using a combination of bipolar and field-effect transistors · CPC title

• H04L25/06

  DC level restoring means; Bias distortion correction {; Decision circuits providing symbol by symbol detection} · CPC title

• H04B3/00 Primary

  Line transmission systems (combined with near-field transmission systems H04B5/00) · CPC title