Continuous time linear equalizer that uses cross-coupled cascodes and inductive peaking

Patent metadata

Field	Value
Publication number	US-9735989-B1
Application number	US-201615190575-A
Country	US
Kind code	B1
Filing date	Jun 23, 2016
Priority date	Jun 23, 2016
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

The disclosed embodiments relate to the design of an equalizer that uses both cross-coupled cascodes and inductive peaking to reduce distortion in a signal received from a communication channel by attenuating lower frequencies and amplifying higher frequencies. At lower frequencies, when the effects of inductive impedance within the equalizer are negligible, the equalizer essentially functions as a traditional cascode amplifier that presents high gain. At higher frequencies, the increases in inductive impedances within the equalizer act to boost a gain of the equalizer.

First claim

What is claimed is:

1. An equalizer, comprising:
a differential input comprising a first input and a second input;
a differential output comprising a first output and a second output;
a first inductor with a lower terminal and an upper terminal, wherein the upper terminal is coupled to V DD ;
a second inductor with a lower terminal and an upper terminal, wherein the upper terminal is coupled to V DD ;
a first resistor with an upper terminal and a lower terminal, wherein the upper terminal is coupled to the lower terminal of the first inductor;
a second resistor with an upper terminal and a lower terminal, wherein the upper terminal is coupled to the lower terminal of the second inductor;
a first cascode comprising a first upper transistor and a first lower transistor, wherein a drain of the first upper transistor is coupled to the lower terminal of the first resistor and the first output, wherein a gate of the first upper transistor is cross-coupled to the lower terminal of the second inductor, wherein a source of the first upper transistor is coupled to a drain of the first lower transistor, and wherein a gate of the first lower transistor is coupled to the first input;
a second cascode comprising a second upper transistor and a second lower transistor, wherein a drain of the second upper transistor is coupled to the lower terminal of the second resistor and the second output, wherein a gate of the second upper transistor is cross-coupled to the lower terminal of the first inductor, wherein a source of the second upper transistor is coupled to a drain of the second lower transistor, and wherein a gate of the second lower transistor is coupled to the second input;
a first current source coupled between a source of the first lower transistor and ground; and
a second current source coupled between a source of the second lower transistor and ground.

2. The equalizer of claim 1 , further comprising a source-degeneration resistor coupled between the source of the first lower transistor and the source of the second lower transistor.

3. The equalizer of claim 1 , wherein the first upper transistor, the first lower transistor, the second upper transistor and the second lower transistor comprise nanoscale FinFET devices.

4. The equalizer of claim 1 , wherein increased impedances of the first and second inductors at higher frequencies act to boost a gain of the equalizer at the higher frequencies.

5. The equalizer of claim 1 , wherein the equalizer comprises a continuous time linear equalizer.

6. The equalizer of claim 1 , wherein a differential signal that feeds into the differential input is received from a communication channel.

7. The equalizer of claim 1 , wherein the first and second inductors, the first and second resistors, the first and second cascodes and the first and second current sources are integrated onto a single semiconductor chip.

8. A system, comprising:
at least one processor;
at least one memory coupled to the at least one processor; and
an equalizer that facilitates communications among components in the system, wherein the equalizer includes:
a differential input comprising a first input and a second input;
a differential output comprising a first output and a second output;
a first inductor with a lower terminal and an upper terminal, wherein the upper terminal is coupled to V DD ;
a second inductor with a lower terminal and an upper terminal, wherein the upper terminal is coupled to V DD ;
a first resistor with an upper terminal and a lower terminal, wherein the upper terminal is coupled to the lower terminal of the first inductor;
a second resistor with an upper terminal and a lower terminal, wherein the upper terminal is coupled to the lower terminal of the second inductor;
a first cascode comprising a first upper transistor and a first lower transistor, wherein a drain of the first upper transistor is coupled to the lower terminal of the first resistor and the first output, wherein a gate of the first upper transistor is cross-coupled to the lower terminal of the second inductor, wherein a source of the first upper transistor is coupled to a drain of the first lower transistor, and wherein a gate of the first lower transistor is coupled to the first input;
a second cascode comprising a second upper transistor and a second lower transistor, wherein a drain of the second upper transistor is coupled to the lower terminal of the second resistor and the second output, wherein a gate of the second upper transistor is cross-coupled to the lower terminal of the first inductor, wherein a source of the second upper transistor is coupled to a drain of the second lower transistor, and wherein a gate of the second lower transistor is coupled to the second input;
a first current source coupled between a source of the first lower transistor and ground; and
a second current source coupled between a source of the second lower transistor and ground.

9. The system of claim 8 , further comprising a source-degeneration resistor coupled between the source of the first lower transistor and the source of the second lower transistor.

10. The system of claim 8 , wherein the first upper transistor, the first lower transistor, the second upper transistor and the second lower transistor comprise nanoscale FinFET devices.

11. The system of claim 8 , wherein increased impedances of the first and second inductors at higher frequencies act to boost a gain of the equalizer at the higher frequencies.

12. The system of claim 8 , wherein the equalizer comprises a continuous time linear equalizer.

13. The system of claim 8 , wherein a differential signal that feeds into the differential input is received from a communication channel that facilitates communications among the components in the system.

14. The system of claim 8 , wherein the first and second inductors, the first and second resistors, the first and second cascodes and the first and second current sources are integrated onto a single semiconductor chip within the system.

Assignees

• Oracle Int Corp

Inventors

• Xie Jingqiong
• Krishnamoorthy Ashok V
• Zheng Xuezhe
• Denq Jeffrey W
• Raj Kannan

Classifications

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• H03F3/45188

  Non-folded cascode stages · CPC title

• H04B1/123

  using adaptive balancing or compensation means (adaptive filter circuits and algorithms H03H) · CPC title

• H04B3/14

  characterised by the equalising network used · CPC title

• H03F3/45201

  Non-folded cascode stages · CPC title