Harmonic filtering for high power radio frequency (RF) communications

Patent metadata

Field	Value
Publication number	US-11349448-B2
Application number	US-201916586153-A
Country	US
Kind code	B2
Filing date	Sep 27, 2019
Priority date	Sep 27, 2019
Publication date	May 31, 2022
Grant date	May 31, 2022

Abstract

Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. For disclosed embodiments, a filter circuit is coupled between a first internal node and a connection pad for an integrated circuit. The filter circuit includes a first inductance, a variable capacitance, and a second inductance. The capacitance amount for the variable capacitance is controlled to tune filtering for the filter circuit to a harmonic of a frequency for a transmit output signal. A power amplifier outputs the transmit output signal to the connection pad without passing through the filter circuit. The filter circuit filters the harmonic of the frequency for the transmit output signal, shunting harmonic current to ground. For one embodiment, the filtered harmonic is a third harmonic of the transmit frequency. For one embodiment, the transmit output signal has an output power greater than or equal to 15 dBm.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a filter circuit coupled between a first node and a connection pad for the integrated circuit, the filter circuit comprising:
a first inductance coupled between the first node and a second node;
a variable capacitance coupled between the second node and ground; and
a second inductance coupled between the second node and the connection pad;

a power amplifier coupled, during a transmit mode, to provide a transmit output signal having a transmit frequency to the connection pad without passing through the filter circuit; and
a controller coupled, during the transmit mode, to control a capacitance amount for the variable capacitance included within the filter circuit, wherein the capacitance amount is controlled by the controller to tune the filter circuit to a harmonic of the transmit frequency of the transmit output signal provided by the power amplifier during the transmit mode; and
wherein the filter circuit filters the harmonic of the transmit frequency from the transmit output signal provided by the power amplifier during the transmit mode by shunting a harmonic current associated with the harmonic of the transmit frequency through the filter circuit to the ground.

2. The integrated circuit of claim 1 , wherein the harmonic is a third harmonic of the transmit frequency for the transmit output signal.

3. The integrated circuit of claim 1 , further comprising a switch coupled between the first node and ground, and wherein the controller is configured to provide a control signal to the switch to cause the switch to be open in a receive mode and closed in the transmit mode.

4. The integrated circuit of claim 3 , further comprising a low noise amplifier coupled to the first node to receive a receive signal from the filter circuit during the receive mode.

5. The integrated circuit of claim 1 , wherein two separate inductor structures are used to provide the first inductance and the second inductance, or wherein a tapped inductor structure is used to provide the first inductance and the second inductance.

6. The integrated circuit of claim 1 , wherein the power amplifier is configured to generate output power for the transmit output signal of greater than or equal to 15 dBm.

7. The integrated circuit of claim 1 , wherein the variable capacitance comprises a plurality of capacitors coupled to a plurality of switches that receive control signals from the controller.

8. A system, comprising:
an antenna;
an integrated circuit having a receive path including a low noise amplifier (LNA) and a transmit path including a power amplifier;
one or more bond wires coupled between an on-chip radio frequency (RF) input/output pad for the integrated circuit and an off-chip RF input/output pad coupled to the antenna;
a filter circuit within the integrated circuit coupled between the LNA and the on-chip RF input/output pad, the filter circuit comprising:
a first inductance coupled between the LNA and a second node;
a variable capacitance coupled between the second node and ground; and
a second inductance coupled between the second node and the on-chip RF input/output pad; and

a controller coupled to control a capacitance amount for the variable capacitance;
wherein the power amplifier is coupled, during a transmit mode, to provide a transmit output signal at a transmit frequency to the RF input/output pad without passing through the filter circuit;
wherein the controller is configured, during the transmit mode, to tune the filter circuit to a harmonic of the transmit frequency of the transmit output signal provided by the power amplifier during the transmit mode; and
wherein the filter circuit filters the harmonic of the transmit frequency from the transmit output signal provided by the power amplifier during the transmit mode by shunting a harmonic current associated with the harmonic of the transmit frequency through the filter circuit to the ground.

9. The system of claim 8 , wherein the harmonic is a third harmonic of the transmit frequency of the transmit output signal.

10. The system of claim 8 , further comprising a switch coupled between ground and a node between the LNA and the first inductance, and wherein the controller is configured to provide a control signal to the switch to cause the switch to be open in a receive mode and closed in the transmit mode.

11. The system of claim 8 , wherein two separate inductor structures are used to provide the first inductance and the second inductance, or wherein a tapped inductor structure is used to provide the first inductance and the second inductance.

12. The system of claim 8 , wherein the power amplifier is configured to generate output power for the transmit output signal of greater than or equal to 15 dBm.

13. The system of claim 8 , wherein the variable capacitance comprises a plurality of capacitors coupled to a plurality of switches that receive control signals from the controller.

14. A method to operate an integrated circuit, comprising:
providing a filter circuit and a power amplifier within the integrated circuit, the filter circuit being coupled between a first node and a connection pad for the integrated circuit and the filter circuit comprising:
a first inductance coupled between the first node and a second node;
a variable capacitance coupled between the second node and ground; and
a second inductance coupled between the second node and the connection pad;

outputting a transmit output signal at a transmit frequnecy, during a transmit mode, from the power amplifier to the connection pad without passing through the filter circuit;
controlling a capacitance amount for the variable capacitance to tune the filter circuit to a harmonic of the transmit frequency of the transmit output signal output by the power amplifier during the transmit mode; and
filtering the harmonic of the transmit frequency from the transmit output signal with the filter circuit by shunting a harmonic current associated with the harmonic of the transmit frequency through the filter circuit to the ground.

15. The method of claim 14 , wherein the harmonic is a third harmonic of the transmit frequency of the transmit output signal.

16. The method of claim 14 , further comprising closing a switch to couple the first node to ground in the transmit mode and opening the switch to disconnect the first node from ground in a receive mode.

17. The method of claim 16 , further comprising receiving, with a low noise amplifier, a receive signal from the filter circuit during the receive mode.

18. The method of claim 14 , wherein two separate inductor structures are used to provide the first inductance and the second inductance, or wherein a tapped inductor structure is used to provide the first inductance and the second inductance.

19. The method of claim 14 , wherein the outputting comprises generating the transmit output signal having an output power greater than or equal to 15 dBm.

20. The method of claim 14 , further comprising controlling the capacitance amount by adjusting controls signals to a plurality of switches coupled to a plurality of capacitors.

Assignees

• Silicon Lab Inc

Inventors

• Sun Ruifeng
• Barale Francesco
• Jayakumar Vinod
• Wu Sherry Xiaohong
• Koroglu Mustafa H
• Atalla Essam S

Classifications

• H04B2001/0408

  with power amplifiers · CPC title

• H03H2210/025

  Capacitor · CPC title

• H03F2200/171

  A filter circuit coupled to the output of an amplifier · CPC title

• H03F1/565

  using inductive elements · CPC title

• H03H7/1766

  Parallel LC in series path (H03H7/1783 takes precedence) · CPC title