Digital filtering using combined approximate summation of partial products

Patent metadata

Field	Value
Publication number	US-11347476-B2
Application number	US-202017067056-A
Country	US
Kind code	B2
Filing date	Oct 9, 2020
Priority date	Oct 9, 2020
Publication date	May 31, 2022
Grant date	May 31, 2022

Abstract

Digital filters and filtering methods may employ truncation, internal rounding, and/or approximation in a summation circuit that combines multiple sets of bit products arranged by bit weight. One illustrative digital filter includes: a summation circuit coupled to multiple partial product circuits. Each partial product circuit is configured to combine bits of a filter coefficient with bits of a corresponding signal sample to produce a set of partial products. The summation circuit produces a filter output using a carry-save adder (“CSA”) tree that combines the partial products from the multiple partial product circuits into bits for two addends. The CSA tree has multiple lanes of adders, each lane being associated with a corresponding bit weight. The adders in one or more of the lanes associated with least significant bits of the filter output are approximate adders that trade accuracy for simpler implementation. In an illustrative receiver, the filter is coupled to a decision element that derives a sequence of symbol decisions.

First claim

What is claimed is:

1. A receiver that comprises:
a digital filter including:
multiple partial product circuits, each partial product circuit configured to combine bits of a filter coefficient with bits of a corresponding signal sample to produce a set of partial products; and
a summation circuit coupled to the multiple partial product circuits to produce a filter output using a carry-save adder (“CSA”) tree that combines the partial products from the multiple partial product circuits into bits for two addends, the CSA tree having multiple lanes of adders, each lane being associated with a corresponding bit weight, the adders in one or more of the lanes associated with least significant bits of the filter output being approximate adders; and

a decision element that derives a sequence of symbol decisions based at least in part on the filter output.

2. The receiver of claim 1 , wherein the filter coefficients include feed forward equalization (“FFE”) filter coefficients and at least one feedback filter coefficient.

3. The receiver of claim 1 , wherein the decision element comprises a slicer for four-level pulse amplitude modulation (PAM4).

4. The receiver of claim 1 , wherein the decision element includes a multiplexing arrangement coupled to a precompensation unit.

5. The receiver of claim 1 , wherein the summation circuit further includes a carry-propagate adder (“CPA”) that sums the two addends to form the filter output, the CPA having an adder for each overlapping bit weight of the two addends, wherein the CPA adders associated with said one or more lanes associated with least significant bits are approximate adders.

6. The receiver of claim 1 , wherein the multiple partial product circuits omit any partial products associated with a bit weight below a predetermined rounding level, the predetermined rounding level being greater than the bit weight associated with a partial product of a least significant bit of a filter coefficient with a least significant bit of a corresponding signal sample.

7. The receiver of claim 6 , wherein the predetermined rounding level corresponds to a number of internal rounding bits R, and wherein the summation circuit truncates at least one least significant bit from a sum of the two addends when producing the filter output.

8. The receiver of claim 1 , wherein the adders in at least five lanes associated with the most significant bits of the filter output are accurate adders.

9. The receiver of claim 1 , wherein the signal samples are separated in space.

10. The receiver of claim 1 , wherein the signal samples are separated in time.

11. A receiving method that comprises:
for each of multiple filter coefficients, combining bits of the filter coefficient with bits of a corresponding signal sample using multiple partial product circuits to produce a set of partial products;
producing a filter output using a carry-save adder (“CSA”) tree that combines the partial products from the multiple sets into bits for two addends, the CSA tree having multiple lanes of adders, each lane being associated with a corresponding bit weight, the adders in one or more of the lanes associated with least significant bits of the filter output being approximate adders; and
using a decision element to derive a sequence of symbol decisions based at least in part on the filter output.

12. The receiving method of claim 11 , wherein the bit weights associated with said one or more of the lanes limit statistical noise of the approximate adders to a power level at or below a noise power level in the signal samples.

13. The receiving method of claim 11 , wherein said using a decision element to derive includes comparing the filter output to one or more decision thresholds.

14. The receiving method of claim 13 , wherein said one or more decision thresholds include precompensation.

15. The receiving method of claim 11 , wherein said using a decision element to derive includes combining the filter output with a feedback signal and comparing the combined signal to one or more decision thresholds.

16. The receiving method of claim 11 , wherein said producing further employs a carry-propagate adder (“CPA”) that sums the two addends to form the filter output, the CPA having an adder for each overlapping bit weight of the two addends, wherein the CPA adders associated with said one or more lanes are approximate adders.

17. The receiving method of claim 11 , wherein each set of partial products omits any partial products associated with a bit weight below a predetermined rounding level, the predetermined rounding level being greater than the bit weight associated with a partial product of a least significant bit of a filter coefficient with a least significant bit of a corresponding signal sample.

18. The receiving method of claim 17 , wherein the predetermined rounding level corresponds to a number of internal rounding bits R, and wherein said producing includes truncating at least one least significant bit from a sum of the two addends.

19. The receiving method of claim 11 , wherein the adders in at least five lanes associated with most significant bits of the filter output are accurate adders.

Assignees

• Credo Tech Group Ltd

Inventors

• Luo Tianchen
• Sun Junqing
• Qian Haoli

Classifications

• G06F7/50

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title

• G06F7/523 Primary

  Multiplying only · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title