Interconnected command/address resources

Patent metadata

Field	Value
Publication number	US-11342042-B2
Application number	US-202016836646-A
Country	US
Kind code	B2
Filing date	Mar 31, 2020
Priority date	Mar 31, 2020
Publication date	May 24, 2022
Grant date	May 24, 2022

Abstract

Command/address (CA) pads of a wafer may be coupled with one or more logic circuits of the wafer to support transmission of a test signal between different memory dies of the wafer. A CA pad of a first memory die may be coupled with a repeater circuit in a scribe region of the wafer, and the repeater circuit may be coupled with a corresponding control circuit in the scribe region. These circuits may support repetition of a signal from a probe card to one or more other CA conductive paths of one or more other memory dies of the wafer. The repeater circuit may receive a test signal from the CA pad, which may be coupled with and receive the test signal from the probe card, and may transmit the test signal to another CA pad of another memory die based on a configuration of the control circuit.

First claim

What is claimed is:

1. An apparatus, comprising:
a first memory die comprising:
a first command/address pad for receiving a signal from a probe card; and
a first command/address conductive path coupled with the first command/address pad;

a second memory die comprising a second command/address conductive path; and
a logic circuit in a region positioned between the first memory die and the second memory die, the logic circuit configured to selectively couple the first command/address conductive path of the first memory die with the second command/address conductive path of the second memory die and selectively isolate the first command/address conductive path of the first memory die from the second command/address conductive path of the second memory die.

2. The apparatus of claim 1 , wherein the logic circuit comprises a first circuit coupled with and configured to selectively communicate the signal between the first command/address conductive path and the second command/address conductive path.

3. The apparatus of claim 2 , wherein the logic circuit further comprises a second circuit coupled with the first circuit, the first command/address conductive path, and the second command/address conductive path, the second circuit configured to control the first circuit to selectively communicate the signal.

4. The apparatus of claim 3 , wherein:
the first memory die further comprises a first signal pad for receiving a second signal from the probe card, the first signal pad coupled with the second circuit; and
the second memory die further comprises a second signal pad for receiving a third signal from the probe card, the second signal pad coupled with the second circuit.

5. The apparatus of claim 1 , further comprising:
a layer of material for routing signals to a plurality of memory dies that comprises the first memory die and the second memory die, the layer of material coupled with the plurality of memory dies;
a plurality of command/address pads located in the layer of material, the plurality of command/address pads comprising the first command/address pad; and
a plurality of command/address conductive paths located in the layer of material, the plurality of command/address conductive paths comprising the first command/address conductive path and the second command/address conductive path.

6. An apparatus comprising:
a first memory die comprising:
a first command/address pad for receiving a signal from a probe card; and
a first command/address conductive path coupled with the first command/address pad;

a second memory die comprising a second command/address conductive path;
a logic circuit in a region positioned between the first memory die and the second memory die, the logic circuit configured to selectively couple the first command/address conductive path of the first memory die with the second command/address conductive path of the second memory die;
a third memory die comprising a third command/address conductive path; and
a second logic circuit in a second region positioned between the second memory die and the third memory die, the second logic circuit configured to selectively couple the second command/address conductive path of the second memory die with the third command/address conductive path of the third memory die.

7. The apparatus of claim 6 , wherein the second logic circuit comprises a third circuit coupled with and configured to selectively communicate the signal between the second command/address conductive path and the third command/address conductive path.

8. The apparatus of claim 7 , wherein the first command/address conductive path, the logic circuit, the second command/address conductive path, and the second logic circuit are configured to selectively communicate the signal between the first command/address conductive path and the third command/address conductive path.

9. A method, comprising:
receiving, at a wafer that comprises a plurality of memory dies, a first signal indicating a test configuration of the wafer;
receiving, from a probe card, a second signal at a first command/address conductive path of a first memory die of the plurality of memory dies;
determining, at a first logic circuit of the wafer, to communicate the second signal from the first command/address conductive path of the first memory die to a second command/address conductive path of a second memory die of the plurality of memory dies based at least in part on the test configuration; and
communicating, using the first logic circuit, the second signal from the first command/address conductive path of the first memory die to the second command/address conductive path of the second memory die based at least in part on determining to communicate the second signal to the second memory die.

10. The method of claim 9 , further comprising:
determining, at a second logic circuit of the wafer, to communicate the second signal to a third command/address conductive path of a third memory die of the plurality of memory dies based at least in part on the test configuration; and
communicating, using the second logic circuit, the second signal to the third command/address conductive path of the third memory die based at least in part on determining to communicate the second signal to the third memory die.

11. The method of claim 9 , wherein communicating the second signal to the second command/address conductive path comprises:
communicating the second signal via a first subset of the first logic circuit, the first subset of the first logic circuit coupled with the first command/address conductive path and the second command/address conductive path.

12. The method of claim 11 , further comprising:
generating, at a second subset of the first logic circuit and based at least in part on determining to communicate the second signal to the second command/address conductive path, a control signal for the first subset of the first logic circuit to transmit the second signal to the second command/address conductive path; and
communicating the control signal with the first subset of the first logic circuit, wherein communicating the second signal via the first subset of the first logic circuit is based at least in part on communicating the control signal with the first subset of the first logic circuit.

13. The method of claim 11 , further comprising:
generating, at a second subset of the first logic circuit and based at least in part on determining to communicate the second signal to the second command/address conductive path, a control signal for the first subset of the first logic circuit to transmit the second signal to the second command/address conductive path; and
communicating the control signal with the first subset of the first logic circuit, wherein communicating the second signal via the first subset of the first logic circuit is based at least in part on communicating the control signal with the first subset of the first logic circuit.

14. The method of claim 9 , further comprising:
determining, at a second logic circuit of the wafer, to suppress communication of the second signal to a third command/address conductive path of a third memory die of the plurality of memory dies based at least in part on the test configuration; and
suppressing communication of the second signal from the second command/address conductive path to the third command/address conductive path using the second logic circuit and based at least in part on determining to suppress communication of the second signal to the third memory die.

15. The method of claim 14 , wherein determining to suppress communication of the secon

Assignees

• Micron Technology Inc

Inventors

• Johnson Jason M
• Fujiwara Yoshinori
• Werhane Kevin G

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• G11C2029/1206

  Location of test circuitry on chip or wafer · CPC title

• G11C29/48 Primary

  Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths · CPC title