Integrated circuit with programmable input/output module

Patent metadata

Field	Value
Publication number	US-11340995-B2
Application number	US-202016879905-A
Country	US
Kind code	B2
Filing date	May 21, 2020
Priority date	May 21, 2020
Publication date	May 24, 2022
Grant date	May 24, 2022

Abstract

An integrated circuit includes a processing core, memory coupled to the processing core, a plurality of pins, an input/output (IO) control module operably coupled to provide control signaling indicating desired functions for the plurality of pins, and a plurality of programmable IO interface modules. A programmable IO interface module includes: a front-end module coupled to at least one pin of the plurality of pins, a back-end module coupled to at least one of the processing core and the memory, and an IO configuration module coupled to the IO control module. Each of the front-end module and the back-end module are configurable, via the control signaling, to configure the at least one pin to operate as one of: a bidirectional interface, an input, an output, a concurrent drive & sense interface, and a concurrent transmit-receive data interface.

First claim

What is claimed is:

1. An integrated circuit comprises:
a processing core;
memory coupled to the processing core;
a plurality of pins;
an input/output (IO) control module operably coupled to provide control signaling indicating desired functions for the plurality of pins; and
a plurality of programmable IO interface modules, wherein a programmable IO interface module of the plurality of programmable IO interface modules includes:
a front-end module coupled to at least one pin of the plurality of pins;
a back-end module coupled to at least one of the processing core and the memory; and
an IO configuration module coupled to the IO control module, wherein each of the front-end module and the back-end module are configurable, via the control signaling, such that the at least one pin is operable to be configured as:
a bidirectional interface;
an input;
an output;
a concurrent drive & sense interface, wherein the concurrent drive & sense interface generates a drive signal and obtains sensed data concurrently on the at least one pin; and
a concurrent transmit-receive data interface.

2. The integrated circuit of claim 1 , wherein the front-end module includes:
a configurable drive-sense circuit; and
a drive-sense circuit signaling circuit, wherein the drive-sense circuit signaling circuit is configurable, via the control signaling, to generate a signal that includes one or more of:
a direct current (DC) signal component;
an oscillating signal component; and
a transmit data reference signal.

3. The integrated circuit of claim 2 further comprises:
when the desired function of the at least one pin is as the input, the configurable drive-sense circuit is configured, based on the control signaling, as one of:
a non-inverting operational amplifier;
an inverting operational amplifier; and
a differential operational amplifier.

4. The integrated circuit of claim 2 further comprises:
when the desired function of the at least one pin is as the output, the configurable drive-sense circuit is configured, via the control signaling, as one of:
a voltage output; and
an output driver.

5. The integrated circuit of claim 2 further comprises:
when the desired function of the at least one pin is as the bidirectional interface, the configurable drive-sense circuit is configured, via the control signaling, as a bidirectional switch.

6. The integrated circuit of claim 2 , wherein when the desired function of the at least one pin is as the concurrent drive & sense interface, the configurable drive-sense circuit is configured, via the control signaling, as a first IO front-end circuit configured to:
generate the drive signal on the at least one pin;
compare a reference signal generated by the drive-sense signaling circuit with the drive signal to detect a change to the drive signal; and
generate a sense signal representative of the change to the drive signal as the sensed data, wherein the sensed data is obtained via the at least one pin concurrently with generating the drive signal on the at least one pin.

7. The integrated circuit of claim 6 , wherein the reference signal includes the DC signal component and the oscillating signal component.

8. The integrated circuit of claim 2 , wherein when the desired function of the at least one pin is as the concurrent transmit-receive data interface, the configurable drive-sense circuit is configured, via the control signaling, as a second IO front-end circuit configured to:
generate a transmit signal on the at least one pin;
compare the transmit data reference signal generated by the drive-sense signaling circuit with the transmit signal to detect a change to the transmit signal; and
generate a signal representative of the change to the transmit signal as a receive signal.

9. The integrated circuit of claim 8 , wherein the transmit data reference signal includes one of:
a digital signal;
an adjusted digital signal;
an analog signal;
a modulated analog signal;
a direct current (DC) adjusted analog signal; and
a modulated, DC adjusted analog signal.

10. The integrated circuit of claim 1 , wherein the back-end module is configurable, based on the control signaling, as one or more of:
an inverter;
a digital to analog converter;
an analog to digital converter;
a digital filter;
a gain circuit;
a level shift circuit;
a transmit-receive data formatting circuit;
a bidirectional switch;
a buffer;
a delay circuit; and
a differential operational amplifier.

11. The integrated circuit of claim 1 , wherein the configuration of the back-end module is based on one or more of:
a desired data format;
a configuration of the front-end module;
compatibility of the programmable IO interface module with other components of the integrated circuit; and
data synchronization of the integrated circuit.

12. The integrated circuit of claim 1 , wherein the front-end module and back-end modules are configurable to operate as one of:
a digital to digital output interface;
an analog to analog output interface;
an analog to digital output interface;
a digital to analog output interface;
a digital to digital input interface;
an analog to analog input interface;
an analog to digital input interface; and
a digital to analog input interface.

13. The integrated circuit of claim 1 further comprises:
a bus coupled to the programmable IO interface module and at least one of the processing core or the memory.

14. The integrated circuit of claim 13 , wherein the programmable IO interface module includes:
a first switching matrix operable to, based on the control signaling, selectively couple the at least one pin to a selected configuration of the front-end module;
a second switching matrix operable to, based on the control signaling, selectively couple the selected configuration of the front-end module to a selected configuration of the back-end module; and
a third switching matrix operable to, based on the control signaling, selectively couple the selected configuration of the back-end module to the bus.

15. An integrated circuit comprises:
a processing core;
memory coupled to the processing core;
a plurality of pins;
an input/output (IO) control module operably coupled to provide control signaling indicating desired functions for the plurality of pins; and
a plurality of programmable IO interface modules, wherein a programmable IO interface module of the plurality of programmable IO interface modules includes:
a front-end module;
a first switching matrix operable to, based on the control signaling, selectively couple at least one pin of the plurality of pins to a selected configuration of the front-end module;
a back-end module;
a second switching matrix operable to, based on the control signaling, selectively couple the selected configuration of the front-end module to a selected configuration of the back-end module; and
a third switching matrix operable to, based on the control signaling, selectively couple the selected configuration of the back-end module to a bus of the integrated circuit, wherein the bus is coupled to at least one of the processing core and the memory, and wherein the front-end module and back-end module are selectively configured based on the control signaling such that the at least one pin is configurable as:
a bidirectional interface;
an input;
an output;
a concurrent drive & sense interface, wherein the concurrent drive & sense interface generates a drive signal and obtains sensed data concurrently on the at least one pin; and
a concurrent transmit-receive data interface.

Assignees

• Sigmasense Llc

Inventors

• Seger Jr Richard Stuart
• Morrison Gerald Dale
• Van Ostrand Daniel Keith
• Gray Patrick Troy
• Markison Timothy W

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/105 Primary

  where the program performs an input/output emulation function · CPC title

• G06F11/1443 Primary

  Transmit or communication errors · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title

• H04L1/0057

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title