Internal clock distortion calibration using DC component offset of clock signal

Patent metadata

Field	Value
Publication number	US-11336265-B2
Application number	US-202117214262-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Dec 20, 2017
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

First claim

We claim:

1. Circuitry, comprising:
an input buffer;
a comparator;
a low pass filter electrically coupling the input buffer to the comparator;
a state machine electrically coupled to an output of the comparator; and
a buffer separate from and electrically coupled indirectly to the input buffer, wherein the buffer electrically couples an output of the input buffer to an input of the low pass filter.

2. The circuitry of claim 1 , wherein:
the input buffer is a first input buffer, the low pass filter is a first low pass filter, and the buffer is a first buffer;
an output of the low pass filter is electrically coupled to a first input of the comparator; and
the circuitry further comprises:
a second input buffer,
a second low pass filter electrically coupling the second input buffer to the comparator, wherein an output of the second low pass filter is electrically coupled to a second input of the comparator, and
a second buffer separate from and electrically coupled indirectly to the second input buffer, wherein the second buffer electrically couples an output of the second input buffer to an input of the second low pass filter.

3. The circuitry of claim 1 , wherein:
the input buffer is a first input buffer and is configured to receive a first voltage signal;
the circuitry further comprises a second input buffer configured to receive a second voltage signal separate from the first voltage signal; and
the first input buffer is configured to receive the first voltage signal without receiving the second voltage signal, or the second input buffer is configured to receive the second voltage signal without receiving the first voltage signal.

4. The circuitry of claim 1 , wherein:
the input buffer is a first input buffer;
the circuitry further comprises a second input buffer and biasing circuitry;
the biasing circuitry electrically couples the state machine to the first and second input buffers;
the biasing circuitry includes a first output and a second output; and
the first input buffer is electrically coupled to the first output of the biasing circuitry but not to the second output of the biasing circuit, or the second input buffer is electrically coupled to the second output of the biasing circuitry but not to the first input of the biasing circuitry.

5. The circuitry of claim 1 , wherein the comparator is an auto-zeroing comparator.

6. The circuitry of claim 1 , wherein the state machine is electrically coupled directly to an output of an operational amplifier of the comparator.

7. The circuitry of claim 1 , wherein the state machine is configured to perform a bisectional sweep algorithm or a binary search based at least in part on a signal received via the output of the comparator.

8. The circuitry of claim 1 , wherein:
the circuitry is electrically coupled to an internal clock pathway of an electrical circuit die;
an input of the buffer of the circuitry is electrically coupled to a node of the internal clock pathway; and
the node corresponds to a point along the internal clock pathway that is farthest from an input of the internal clock pathway before the internal clock pathway branches in two or more directions to other integrated circuitry of the electrical circuit die.

9. The circuitry of claim 1 , wherein:
the circuitry further comprises biasing circuitry electrically coupling the state machine to an input of the input buffer; and
the input buffer is configured to calibrate a duty cycle of a voltage signal based at least in part on a signal output from the biasing circuitry.

10. The circuitry of claim 1 , further comprising a multiplexer electrically coupling an output of the low pass filter to an input of the comparator.

11. Calibration circuitry, comprising:
a first input buffer;
a second input buffer;
a first low pass filter electrically coupled to the first input buffer;
a second low pass filter electrically coupled to the second input buffer;
a comparator having a first input and a second input electrically coupled to the first low pass filter and the second low pass filter, respectively;
biasing circuitry electrically coupled to an output of the comparator, wherein the biasing circuitry includes a first output and a second output, wherein an input of the first input buffer is electrically coupled to the first output of the biasing circuitry but not to the second output of the biasing circuitry, and wherein an input of the second input buffer is electrically coupled to the second output of the biasing circuitry but not to the first output of the biasing circuitry.

12. The calibration circuitry of claim 11 , wherein:
an input of the first low pass filter is electrically coupled to an output of the first input buffer but not to an output of the second input buffer; or
an input of the second low pass filter is electrically coupled to an output of the second input buffer but not to an output of the first input buffer.

13. The calibration circuitry of claim 11 , further comprising:
a first buffer separate from the first input buffer and the second input buffer, wherein the first buffer electrically couples the first input buffer to the first low pass filter; or
a second buffer separate from the first input buffer and the second input buffer, wherein the second buffer electrically couples the second input buffer to the second low pass filter.

14. The calibration circuitry of claim 11 , wherein:
the first input buffer is configured to receive a first voltage signal;
the second input buffer is configured to receive a second voltage signal without receiving the first voltage signal; and
the second voltage signal is complementary to the first voltage signal.

15. The calibration circuitry of claim 11 , further comprising a state machine electrically coupling the comparator to the biasing circuitry.

16. The calibration circuitry of claim 15 , wherein an input of the state machine is electrically coupled directly to an output of an operational amplifier of the comparator.

17. The calibration circuitry of claim 11 , wherein the comparator is an auto-zeroing comparator.

18. Clock distortion calibration circuitry, comprising:
a low pass filter configured to obtain a first direct current (dc) level representation of a first duty cycle of a clock signal;
a comparator electrically coupled to the low pass filter, wherein the comparator is configured to compare the first dc level representation to a second dc level representation of a second duty cycle of the clock signal;
a state machine configured to calculate or adjust a trim value associated with the first duty cycle of the clock signal based at least in part on results of the comparison;
biasing circuitry configured to convert the trim value into one or more biasing voltages or one or more biasing currents;
an input buffer configured to (i) receive a voltage signal of the clock signal and (ii) calibrate the first duty cycle of the clock signal using the one or more biasing voltages or the one or more biasing currents; and
a buffer electrically coupled indirectly to the input buffer and electrically coupling the input buffer to the low pass filter.

19. The clock distortion calibration circuitry of claim 18 , wherein:
the low pass filter is a first low pass filter, the input buffer is a first input buffer, the buffer is a first buffer, and the voltage signal is a first voltage signal;
the clock distortion calibration circuitry further comprises:
a second low pass filter configured to obtain the second dc level representation of th

Assignees

• Micron Technology Inc

Inventors

• Wang Guan
• Tang Qiang
• Ghalam Ali Feiz Zarrin

Classifications

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• G06F1/04 Primary

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• H04L7/00

  Arrangements for synchronising receiver with transmitter {(synchronisation of generators of electric oscillations or pulses H03L7/00)} · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• H03K5/22

  Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral (indicating phase difference of two cyclic pulse trains G01R25/00) · CPC title